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I've created schematic using single CLK input.
Then I've changed the input using ibufgds primitive (naturally inputs were renamed to clk_p and clk_n)
Now I want to modify timing constraint to reflect changes. But still there is only clk net available. Moreover there is only clk pin available...
I run the same project once on spartan 3 and then on proasic (actel)
On Xilinx design evironment I received 94.5 MHz estimated frequency (by usuing LUT's).
On Actel design environment (by using RAM) I got 16MHz estimated frequency
Does anyone know what should be considered (in project...
memory in verilog
reg [13] RAM [2];
How big this ram actually is?
is it 14bits by 3 slots
or 14x8 slots ?
by incrementing counter we get cell adresses from 0 to 7 and by shifting 1
we get 3 x 14 bit memory ocupation.
What is right?
I thought that it is 14x3 but after studying the fifo...
I have imported LT op amp simulation sub circuit model from LTSpice library (.mod) file. I did it by simply changing ext from .mod to ckt.
Altium Accepted this model.
However when it came to simulation it looks Altium does not understand SPICE.
The line which cause error:
ESHD1 88 0...
I don't know what You control, but error is always as difference. However, You should calculate system gain. So You have to create open loop, and send range of input signals in whole range (PWM in your case). Note system output, and calcualate gain = So/Si. Then You should repeat experiment from...
Each manufacturing process has a variety of software. If You are interested in names You should browse the web.
About software and PLC , usualy software is distributed with IO hardware . So connecting PLC is pretty straightforward
msp430 i2c programming
registers are not accessible directly from C. You should inline assembly code to access registers. There are also certain rules about C function parameters, like first r15 etc. So You may be aware what register is used.
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