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In Boser and Wooley's classic delta sigma paper it says:
The error caused by clock jitter is inversely proportional to the OSR and since the in-band quantization noise is [b]inversely proportional to the fifth power of OSR, the amount of clock jitter that can be tolerated decreases for an...
xshou,
I believe daniel just wanted to express that he may not cover the whole details in his post and suggested that one can find more details in the book. That's why he keeps mention his English may not be perfect ( whose English is perfect here? we are not marketings, right? :)
On a side...
.stb analysis in spectre
If I am using hspice, how should I break both loops at once? And how do I tell the result is cmfb's loop stability or diff loop's stability? Or am I completely mis-understood?:?:
Thanks!
The opamp is the same architecture as Annovazzi et.'s paper of jsscc july 02. and is used inside for a RC active filter.
Two questions:
1. How many CMFB is needed for this kind of structure? Can we do two cmfb instead of one for his opamp?
2. If I use resistor type of cmfb as sensing ckt...
cmfb noise
Can you explain in more detail? Two stage opamp means the main opamp right? What do you mean to use lower resistances to the cmfb sense?
Thanks!
high linearity follower
Hi all,
I am designing an opamp for audio application. The opamp needs to achieve high linearity and low noise. For high linearity, resistor type of CMFB seems to be a good candidate, but big resistors introduce noise. My question is what kind of CMFB is good to...
My company does not use Cadence and only support hspice.
In active low pass filter, vin to vout is low pass but if I break the loop at the input of opamp and check the loop stability, I get a high pass filter response.
Is the stablity check you run have the same response?
Does that mean in sub-micron design, if you see your transistor's vgs-vth≤0, there is a good chance that the transistor still operates in moderate inversion instead of weak inversion?
Thanks
sample hold circuit opamp
Added after 9 minutes:
I also have seen similar structure in this year's ISSCC paper from Koren authors (sorry I don't have the digest now). It doesn't wast the charge from the input and can run at very high speed. The cons are you can not use bottom plate...
gm/id based analog design method + is it new
hdmi:
There is a new book called:
Tradeoffs and Optimization in Analog CMOS Design (Hardcover)
by David Binkley (Author)
might be helpful to you.
btw, how do you plot gm/id vs IC?
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