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Akhil,
I think I understood what is happen. The operation a>>>b not only do an arithmetic shift, but it also re-size the variable (I did not know that). This is the reason why -27>>3 is treated as 6'b111100 instead of 9'b111111100, which is what I was expecting. Then, because x1[2] is unsigned...
Vijay, I actually got very confused now. In most of the MCS cases, the launch register and capture register has the same enable and clock signal. Thus, hold requirement must be keep unchanged. If I understood correctly, you said that the default behavior of synthesizer is to automatically...
vijay.mani884,
I do not understand why a multicycle hold must be dependent on multicycle setup. Shouldn't a multicycle hold be set only when the conditions for hold violation changes? For example, in case of an interface where output register and input register has same clock, but not aligned...
Pleas some one can explain me why in the below code, x0_eq is not equal to x1_eq?
`timescale 10ns/1ns
module test;
reg signed [8:0] x0, x1, x0_shifted, x0_eq, x1_eq;
initial begin
x0 = -27;
x0_shifted = x0 >>> 3;
x0_eq = x0_shifted + x0[2];
x1 = -27;
x1_eq = (x1 >>> 3) + x1[2]...
Considering the case of two registers connected sequentially. Both have the same clock signal. Both receive an periodic enable signal active in one in every four clock cycles, but the enable signal of one register is delayed by two cycle in relation of the enable signal of the other register...
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