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Recent content by jimway

  1. J

    how to choose cmos device size and bias for digital circuits?

    What do you mean by biasing the digital circuits? If you ment the cml logic, the swing, and common mode voltage will define the tail current.
  2. J

    cmos diff pair mismatch

    The opamp is not fully differential. And according to the amplitude of the mismatch, the systematic mismatch dominated. So the more effecient way is to increase the input common mode range or increase the voltage gain.
  3. J

    I/O transistor vs Analog transistor

    I havn't put it clearly. The following comments are shown in the bsim model file: hints : measurements and parameter fitting in the voltage range: * * |vds| = 0 ... 2.5 (+10%) v : analog mode * |vds| = 0 ... 3.3 (+10%) v : io mode *...
  4. J

    I/O transistor vs Analog transistor

    Could I/O transistor be used to build circuits? What's the difference between I/O transistor and analog one.
  5. J

    cmos diff pair mismatch

    Switching to PMOS pairs and tie the NWELL to the tail won't improve the mismatch alot. The mismatch of diff pair is a function of the overdrive voltage. Try to increase the W/L to lower the Vov, and that might help.
  6. J

    What are the rules for biasing an OP??

    Re: How to bias a OP?? There are several ways to bias high swing cascode current source such as self-biasing.
  7. J

    ask about active filter

    U could trim the current bias of Gm, in Gm-c configuration.
  8. J

    Total harmonic distortion in filter?

    Higher Q has sharp edge which can suppress the higher harmonic. But the higher Qalso introduces the higher group delay. so is there any trade off between Q and THD.
  9. J

    questions about sense amplifier

    Usually SA will introduce the cross coupled load to increase the gain
  10. J

    What is the most commonly used rail-to-rail OP structure??

    the opa with complementary input and class ab output will be rail-to-rail input and output Added after 2 minutes: The configuration proposed by DZC cannot be used as fully differential one.
  11. J

    What are the rules for biasing an OP??

    How to bias a OP?? It depends on the spec like output swing or linearity.
  12. J

    biasing differential amplifier

    biasing analog IC U should set the oppoint by the specs before hand calculation. And the hand calculation can help you to find the bias range.
  13. J

    Question on R-MosFET-C filter

    Hi everyone, I am supposed to design an R-MosFET-C LPF. What has puzzled me is that the corner frequency of R-MosFET-C filter is strongly affacted by the deviation of process. Here is the schematic of the filter. Here is the Bode plot of its corner analysis. My question #1 is how to improve...
  14. J

    How to measure noise of an amplifier?

    Hi, This paper may help u with that question, https://www.evaluationengineering.com/archive/articles/1104/1104looking_into.asp Jim
  15. J

    Discussion on ASITIC and On-chip Transformer Design

    Well, I just wonder whether the 2:1 tramsformer can be replaced by a 1:2 one. The transformer with the ratio of 1:2 can provide the same Lp and Ls when the k is 0.7. To my best knowledge Asitic can only output the s-p of an individual inductor of the transformer while another one is supposed...
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