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Recent content by jianhuachews

  1. J

    Help with coding explaination

    yes. but the thing is i dont understand why.. that means if i don't press on reset, by default, the data is 0000, am i right? i downloaded my program to the board but ringcounter starts without me having to press on reset( which is actually the correct behavior), but i don't understand why does...
  2. J

    Help with coding explaination

    Hi guys can any tell me what does this means?!? if(rst='1') then temp <= (0=> '0', others => '1'); from my understanding, it's supposed to be, bit 0 = '0' when rst = '1', right? i have a ring counter that uses this code but i don't have to hit on a reset button(when pressed =...
  3. J

    Regards to vhdl flipflop

    oh yes it works!!! i didn't know i could program in such a way... thank you for guiding me so much FvM!! :)
  4. J

    Regards to vhdl flipflop

    omg so sorry... it is right i'm not in my right state of mind to do my work now because im sick. Anw yes, thanks! and with regards to what you mentioned i had it changed to process(add) begin if (add='1') then add_op_s <= firstq_s + secondq_s; -- 17 bits <= 16 bits + 16...
  5. J

    Regards to vhdl flipflop

    yes the expression is right! but the output result wasn't. the waveform shows that the output add_op_s and secondq_s are equal. Which is not, because the other signal, firstq_s is at "1111 1111 1111 1111". how can this be happening?!
  6. J

    Regards to vhdl flipflop

    omg sorry my bad! it's done now! but when i simulate it with tb it didn't perform the addition correctly! Can you take a look at it? I've attached a waveform. the expected output for overflow_s and add_op_s is supposed to be '1' and " 1111 1111 1111 1111" after adding firstq_s and secondq_s.
  7. J

    Regards to vhdl flipflop

    Hi guys, can anyone help me with this? Modelsim gave me an error "Cannot resolve slice name as type ieee.std_logic_1164.STD_LOGIC." it's urgent please help! :( process(add) begin if (add='1') then add_op_s (15 downto 0) <= firstq_s + secondq_s; --both firstq_s and secondq_s are...
  8. J

    Regards to vhdl flipflop

    oh yes thanks a lot tricky! i should assign it to a temp signal instead i totally forgot about it. hi FvM, i'm not familiar with buffer... so yea. Thanks for helping, i'd my ff_return_int reset after some modifications. Thanks for the guide! Anyway i've kinda modified my program. can anyone...
  9. J

    Regards to vhdl flipflop

    hi guys, i want to obtain 2outputs ff outputs from the same input driven in. Everytime i press on "ff_return", the ff begins. Below is my program. I tried compiling it but it showed an error in modelsim. Can anyone guide and enlighten me? Thanks in advance. library IEEE; use...
  10. J

    [SOLVED] VHDL 4 digit 7-segment display on nexys 3 board

    Hi guys i've had all my codes done but when i download the program to my board, the four 7-segment shows the same number (lets say i press 3). It wasn't what i intended. i want it to be like when i press a 123 it first shows 1 in the first segment, then 1 in the second segment while 2 in the...
  11. J

    [SOLVED] How to shift 4 bits by 4 bits in 16-bit output data?

    Re: 16-bit shifting vhdl omg thanks i got it!
  12. J

    [SOLVED] How to shift 4 bits by 4 bits in 16-bit output data?

    Re: 16-bit shifting vhdl Hi vipin. I took your advice and created a testbench too. i checked the waveform and it works the way i want. But xilinx ise gave me this error Any suggestions? library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity key_decode is port (...
  13. J

    [SOLVED] How to shift 4 bits by 4 bits in 16-bit output data?

    Hi guys, how do i go about shift 4 bit by 4 bits in a 16-bit output data? for example i have "0000000000000000" then i can only send in 4 bits at a time (lets say i send in "1111" the first time and "1010" the second time) so my output should show something like "0000000000000000" =>...
  14. J

    [SOLVED] Need help with "freezing" data vhdl

    Hi guys, is there anyway i can implement to freeze data from a ring counter? any guidance? library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity column_counter is port ( col_out : out std_logic_vector(3 downto 0); rst : in std_logic; clk ...
  15. J

    [SOLVED] Check my Code for decoder.. need help!

    Hi guys.. Here are all my final codes to my keypad testing. I want my 7seg to show 1 when i press 1 and 2 when i press 2 and so on so forth. But after downloading the program to my board, the 7segment shows a digit '8' and when i pressed the keys on my keypad, nothing is changed. Any help...
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