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I should mention this is a Verilog design but -gfile requires the hierarchy be in VHDL. The hierarchy has a generate array in it as well (which the section on -gfile says you need to use "rounded" parentheses for). So...my hierarchy path is
/top/dut(5)/mymodel/mysubmodel/myparameter
I have a parameter to override that works great in Incisive using -defparam. I'm unable to find an equivalent that works in VCS. Here are the ones I've tried
1. +gfile <file>
the override file contains
assign "new_value_as_string" <path_to_param_to_override>
2. -pvalue...
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