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Recent content by JesseKing

  1. J

    What do the simulators do when elaborating a design?

    so the elabration is just as linking, isn't it ?
  2. J

    How to set multiple license files in flexlm?

    flexlm multiple licenses In winxp how to set multiple license files in flexlm? I'v set several license files in Flexlm manager, separated by ";", but it dosn't work. Flexlm can not recognized them at all. And I'b set several license files for LM_LICENSE_FILE too. There is no conflict, which...
  3. J

    What do the simulators do when elaborating a design?

    And what is the relation of elaboration and compilation? Thanks and regards!
  4. J

    Basic Layout doubt about different delays in 3 parallel signals

    Basic Layout doubt I don't know this very exactly. Let me guess. Maybe sig b is in the middle of the parallel wire group, so both a and can interfere b by crosstalk. Therefore, sig b have more delay than a and c. Change the drive strength of b twice than a and c might overcome this question.
  5. J

    Comparison of Perl and Tcl script languages

    perl regsub comparison but maybe perl is much easier
  6. J

    how assign statement can be implemented?

    I wanna know why problems will occur when PR? Regards!
  7. J

    Metals used for core rings/power strapes in floorplanning?

    Re: floorplan question I always use the top 2 layers for core ring and power straps. but in some design, i found that the top layer was always preserved, why? what is the advantages?
  8. J

    How to optimize this circuit?

    set_structure true is the default option when compiling with DC, you can set_flatten true before compling and you'll get a two-level logic in structure sum-of-product
  9. J

    Verilog RTL and Behavioral Testbench

    agree with thomson. and I want to know why you want to convert your rtl to behavioral level
  10. J

    Metals used for core rings/power strapes in floorplanning?

    floorplan question when floorplanning, which metals should be use for core rings and power strapes? top two layer or bottom two layer? or others ? and what are the advantages and disadvantages of the these stratagems? regards
  11. J

    Where can I find physical complier lab?

    complier lab want to learn using it. Regards!
  12. J

    power consumption in CMOS

    power compiler can tell you the switch power, internal power(short circuit power), both of which are dynamic power. And static power(leakage power) can be caculated too in power compiler.
  13. J

    how to build a non-signed subtractor efficiently

    i know, the function is not hard to understand and it's easy just to build it with a comparator and a traditional complementary adder. what I really want to know is how to implement it efficiently. any advice?
  14. J

    how to build a non-signed subtractor efficiently

    subtract a positive number from another, and use a sign extension format to represent the result, the msb is the sign bit. For example 0011-0010=0001 0010-0011=1001 Can this subtractor be implemented efficiently as a complementry subtractor? Regards!
  15. J

    what is the difference of Registerfile and SRAM?

    I don't think the sram cell can be implemented with 1T, it's a DRAM cell.

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