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Hey guys,
Thanks for your suggestions.
Dominik: I currently have no idea what the selection filter is in Virtuoso, do you have a link to some documentation/video about it and how to use it? I see nothing in my toolbars. I reckon it might actually be usable for other stuff than this as well...
Hey fellow enthusiasts,
I have an annoyance with Cadence Virtuoso schematic viewer. I use border sheet for my designs in an A3 size, to ensure my design sizes don't go out of hand.
However, I wish to move the border sheet to the background or lock it, so I don't continuously mark/move/delete...
Hi Timof
Yes, I am able to run the post-layout simulation. One has to make sure the config file is set up to run the extracted view instead of the ordinary schematic view and; your ADE L / ADE XL must make sure to run the settings from the config file as well.
The simulation time is almost...
Hello everyone. Thank you very much for your assistance, I have solved the issue. It currently works using Calibreview as output file, using either "masklayout" or "schematic" as Calibre view type works splendidly.
Fixing the following errors solved the problems I have been having:
- The wrong...
Hi timof. Thank you very much for your reply.
Interesting regarding the file output. I have recently tried producing a DSPF output and I believe it looks pretty much like it should, even though it is very lengthy. However it does not seem to make any difference, when I try to simulate my DSPF...
Very interesting.
I am running the Calibre Interactive - PEX and not PERC, but I suppose there could be something wrong with our PDK setup.
The pp definitions of resistors and stuff I can clearly see in the calibre view of the extracted schematic, so it must be partly correct I suppoe...
Hello timow thank you for your reply and suggestions.
I have tried simulating my extracted view, did not work unfortunately. And whenever I try to save the calibre view of the extracted layout, I get xxx errors saying floating nodes.
By inspection in the Calibre view I can clearly see the...
Hello jjx
1. The calview.cellmap should be quite fine.
2a. I both pass the standalone LVS and I pass the LVS automatically run when doing a PEX.
2b. Regarding the PEX netlist, I am not 100% sure I am looking at the right one. Current I look at the .pex.netlist file. The list starts out with...
Hello EDAboard
I have been struggling with parasitic extraction using Calibre of my TSMC018 4-stage gate-driver.
Currently I have been unable to find a PDK/tech specific guide to using Calibre for PEX, I have however tried to figure it out myself.
The only issue is now, that the resulting...
1. TSMC foundry has 24 V devices and 36 V. Currently I'm using the 36 V version due to better muCox, otherwise I'd need some shit large transistors.
2. Right, of course.
3. You might be right about this.
Time will tell if it works. This will largely be based on the behaviour of my future...
Hi frankrose, thank you very much for your reply, I greatly appreciate it!
1. Naturally the Vd must be set properly, actually just realised I set it incorrectly in my case. Used 5 V when I should be using 20 V actually.
2. Hmm, I would need to set a DC voltage to set its DC operating region...
Dear everyone
I am currently in midst of designing an integrated switched capacitor converter. But I am having some difficulties assessing MOSFET parasitic capacitances. This both goes for a single NMOS but also CMOS inverters. I am using TSMC018 in Cadence Spectre, to anyone wondering.
I have...
Giving the average current in a capacitor must be zero, it does make sense. But I fail to understand why calculating the average current with the fomula: I_avg = Qgate * fsw does not equal zero.
I was given an excellent idea by looking into the upper leg of my totem-pole driving the MOSFET...
The units are in fact ampere, and not milli or micro. But this large spike happens due to my ideal/fast switching of the MOSFET. But nevertheless, I should be able to get an average of the current.
Even though the average in reality should equal to around 0, due to the charge-second balancing.
Thank you for answering dick_freebird
My issue is, that I currently drive the MOSFETs with ideal gate-drives. This means I have a voltage source connected directly from G-S on my NMOS. Do you know of any to deal with that?
I am trying to do this calculation in order to estimate the...
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