Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I wanted to know why are analog filters built when digital filters can do the same with signal processing. So what inherent benefits does analog signal processing have that their are analog multipliers etc in the market?
What are the advantages of analog signal processing techniques?
@ Keith.....I did not understand that completely.
So if it is a 16 bit ADC.
Does a 4 channel ADC mean that it multiplexes the ADC output into 4 ...4 bit ADCs?
And if you want to use 2 channels the same ADc ..can be made as 2 8bit ADcs?
I know an ADC is used to convert analog to digital signal? It has properties like the sampling rate, the INL, DNL etc. But what does channel mean in a ADC?
Does it mean that a 4 channel ADc has 4 adcs??
I wanted to know what happens when a square wave is applied at one side of capacitor and the other end is open?
In cadence simulation....the output is same as the input.
But what happens in theory? And why does it happen like that?
i agree with Vamsi's answer, that wht i used in my project.
I have included as much schematics as possible.
https://jennisjose.webs.com/pipelinedadc.htm
For the Sample and Hold design ...u can also refer the design explained in Ken Martin.
I have used it in my project and
I have included as much schematics as possible.
The track and hold circuit i used is based on the open loop miller hold capacitance...
Flash ADC is faster. But it si feasible upto 6 bits...beyond that for a good speed u shud go for pipelined ADC.
This is my Amster project report on pipelined ADC design.
I have included as much schematics as possible.
https://jennisjose.webs.com/pipelinedadc.htm
Say if you are designing a 8 bit ADC......u need to have atlest 8 * 6 =48 dB SNDR....6 is a approx constant.
If possible go through MAsabi Abo's thesis paper....
This is my Amster project report on pipelined ADC design.
I have included as much schematics as possible...
The abo thesis is what i went through for my design.
Any ways I m attaching the stuff that I did
This is my Amster project report on pipelined ADC design.
I have included as much schematics as possible.
https://jennisjose.webs.com/pipelinedadc.htm
Your op-amp design doesnt settle in well before the value is fetched.
So either u can make ur switches smaller or ur capacitances larger.
This is my Amster project report on pipelined ADC design.
I have included as much schematics as possible.
https://jennisjose.webs.com/pipelinedadc.htm
This is my Masster project report on pipelined ADC design.
I have included as much schematics as possible.
https://jennisjose.webs.com/pipelinedadc.htm
Diff OpAMP problem
The design of my Masters project operational amplifier is uploaded here. I have a gain of 71 db, PM of 45, and bandwidth of 700Mhz.
https://jennisjose.webs.com/operationalamplifiers.htm
The design of my Masters project operational amplifier is uploaded here. I have a gain of 71 db, PM of 45, and bandwidth of 700Mhz.
https://jennisjose.webs.com/operationalamplifiers.htm
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
