Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by Jaydeep Parmar

  1. J

    VHDL 64 Point FFT using Megacore IP in Altera Quartus II 9.1

    I know this information and what is use of it. but i don't know how to set SOP and EOP to verify the code. and please give me understanding that why they don't have to be used??
  2. J

    VHDL 64 Point FFT using Megacore IP in Altera Quartus II 9.1

    Hey, Can any one say how to use "sink_sop" and "sink_eop" pins in FFT Megacore IP?? Please share VHDL code to control these pins.

Part and Inventory Search

Back
Top