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Hi,
To get gm/id plot you can setup a simulation with the schematic that is showing in the following figure.
Then you must to do a parametric simulation with Vgs as variable. After this, you can use the calculator tool in order
to read the gm and id of the component.
The interpretation is...
Hi,
I don't know its name, but is a basic topology with two stages of gain.
Gain = (gm1gm6/gm3)(ro6||ro8)
Rin = inf.
Rout = ro6||ro8
If you need a more extended explanation about how I obtained these results, you can ask me again.
PD: I assume gm1=gm2 and gm5~8 are equal.
Best Regards.
Hi,
These transistors form an output stage that allows you to have a high output voltage swing. If you keep the output between M14 and M16, for example,
your output voltage swing will be less.
Regards,
Hi!
Well, I think that you are a little bit confused with the meaning of "signal".
The signal is only one component of the total value for a voltage or a current,
the other component is the DC level (bias). When you say that you ADC will work
with input signals between -vref and vref...
Hi,
A High gain in an opamp means that this circuit can amplify smaller
signals than other one with less gain. In other words, High gains
in an opamp limits the amplitud for the input signal.
Look the following simple example:
1. I have an opamp with Gain=100V/V and a Voltage output swing =...
I tried to run DRC rules but ASSURA show me next error:
/usr/local/tools/assura3.16/tools/assura/bin/32bit/assura: error while loading shared libraries: libm.so.6: cannot open shared object file: No such file or directory
But, I have this library!.
Hi,
I must design a power rail supply clamp. I have many options: RC-with 3-inverters, RC- thyristor-delay,
SRAM-based. How can I choose the best?
Best Regards,
Hi,
To avoid confusion, we must have this clear:
A signal represents a wire in the circuit, while a variable is not a physical element. This last one is only used in a process block and help us to execute any code that it requires.
Hi,
Well, that is a cascode current mirror. This topology is implemented in order to eliminate the accuracy-headroom trade-off presented in traditional cascode current mirror. M1 and M2 consumes minimum headroom. You can study this circuit in this book: "Design of Analog CMOS Integrated...
I have a question:
Do you use a explicit current source called idd?, for example:
idd 0 1 1mA
If you try to measure the current, put in the same branch a voltage source with 0V like this:
idd 0 aux 1mA
vdummy aux 1 0V
And put in the .measure statement:
.measure tran integ...
Hi,
Ok, the line with the .include stament is wrong. The correct stament is:
.include 'processo.inc' $$ Note the quotes.
if this does not solve the problem, verify the correct path for the process.inc file. You must put complet path in the .include statement.
Best Regards,
:D
Hi,
You can implemented an output stage with npn and pnp power transistor like shows the next figure. This stage supplies the current for the load. The additional opamp is needed to avoid distortion due to vbe of bjt transistor and to transfer the voltage signal of the primary opamp directly to...
Hi,
I'm an undergraduate student and I'm working in my thesis about esd protection circuits. I had some problems of convergence with simulations. I'm using hspice.
what is the apropiate netlist of the nmos transistor to simulated esd circuits? I readed papers about simulations and the...
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