Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Thank you for the information Ranaya. Question, why do we need the NLDM data? For example, in a liberty file, why can't we only have CCS delay values and not NLDM delay values? Is that a limitation of the characterization?
I've seen liberty files that just have NLDM (Non-linear delay model) data. For the CCS (Composite current source) liberty files I've seen, it always contains NLDM data.
Can a liberty file contain only CCS data and not NLDM data? If not, what is the reason why CCS liberty files must have NLDM data?
Hi all,
I've been coming across some cases where I've been seeing values where Internal Power only has 0 values (whether it be a scalar table or a 1D/2D table with slew/load indices).
Can someone explain to me the reasoning behind the 0 values for Internal Power? My only reasoning could be...
Hi all,
I'm involved in the characterization of Liberty files and I was wondering what are the applications to them outside of STA?
I'm wondering if they are used in Synthesis, possibly using the cell information from PnR. I also understand for Hierarchical Timing Analysis, the Extracted Timing...
For the third dimension (I'm just reading the Liberty User Guide) and the third variable is
Here is what the excerpt says:
Create a three-dimensional table template that uses two variables and indexes to model
transition time and the third variable and index to model load. The variable values...
Hi there,
I've read in the liberty spec that you can add another dimension to the constraint tables (2D setup/hold -> 3D setup/hold)|(1D mpw -> 2D mpw).
The extra dimension is the output load where you can specify the related_output attribute.
How does the output load affect the hold and...
Liberty files: [Input Pin] Capacitance, Rise/Fall Capacitance Ranges Attributes
Hi all,
I'm was trying to understand all aspects of the liberty file and I came across some questions.
I'm looking at the input/inout pin attributes - capacitance, rise/fall capacitance, rise/fall capacitance...
Hi all,
I'd just like some clarifications with some of the capacitance attributes for liberty (.lib) files.
I understand that the rise capacitance and fall capacitance attributes are the capacitance values for the input/inout pin for rising and falling waveforms. I also know that the...
Hello all,
For process corners, what does the NP stand for in SSGNP and FFGNP?
For liberty files, how does this affect the liberty files? Does it make the results more pessimistic or optimistic?
Thanks!
Hello all,
I have a question regarding level shifters. Assuming I have a multi voltage level shifter - 2 voltages; a primary voltage (placed at the top and bottom edge of the level shifter) and a secondary voltage (placed at the center of the level shifter), I was wondering how the rise/fall...
Hello all!
I'm pretty new to ASIC and liberty files and I was wondering if there was a general trend in liberty files and different threshold voltages.
For example, say I'm operating on a library (I'll try to make it as general as possible so std cell, io or memory - any cell, any PVT) and the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.