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formality problem
I'm using Formality to verify the equivalence between RTL and Netlist.
The top module failed because of some failing points in a sub-module ABC.
However, the sub-module ABC can be successfully verified when run singly.
In the top level netlist, the netlist of ABC just be read...
Thanks very much to Thomson and vale, your suggestions helped me a lot ;p
I have two more questions:
1) two modules, one is DELAY coded, I mean, use #1(ns) for example, before each unblocking-assignment, the other one, however, no #1 used. There are some handshakes between the two synchronized...
Any problem if combining a module that use DELAY before unblocking-assignment with another module which do not?
Should the delayed one be one cycle after the un-delayed one, then result in timing dismatch in the combined logic?
thanks any way |-)
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