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Recent content by jameela

  1. J

    little coding required

    i need 16676 posedges of outclk1 during a duration in which a counter k runs from 0 to 1023 can anyone tell a code through which this can be done....??? Added after 4 minutes: i forgot to mention its to be done in verilog
  2. J

    Representing fractional numbers in Verilog

    division in verilog THE ANSWER IS COMING 0 , BUT I WANT IT TO BE IN EXACT FRACTIONS WHAT WOULD BE THE FRACTIONAL BINARY ANS?? HOW CAN I DO IT WITH HELP OF LIBRARIES.....?? Added after 2 minutes: WHAT WOULD BE THE DATA TYPE TO STORE FRACTIONAL NUMBERS?
  3. J

    Representing fractional numbers in Verilog

    e_xk1={1/8}; and e_xk2={-1/8}; 1) what are the resulting values in binary in e_xk1 and e_xk2?? 2) how are they calculated? 3) what should be the correct declarations for e_xk1 and e_xk2?
  4. J

    non repeated random number generator??

    in verilog which function or statement can be used to generate random non repeated numbers between 1 to 1024 using a seed????
  5. J

    is the verilog code correct???

    yes e_xk1 is an output...sory not to mention i tried ur approach using: assign e_xk1 = r[3]; // since all you are doing is divide by 8 == shift by 3. but it gives e_xk1=1 only when r=8.....when r is less than 8 e.g r=7 it gives 0 i want that when r is greater than 4 so e_xk1 should give...
  6. J

    is the verilog code correct???

    i made the input of 5 bits but it cud not help me...result is still all 0
  7. J

    synthesizable verilog divider code required

    can anyone post a synthesizable divider code for 2 variable values??? needed urgently
  8. J

    is the verilog code correct???

    is the following code correct as explained in comments???...its giving zero in both cases....what cud be the alternative? input [3:0]r; reg [3:0] e_xk; reg e_xk1; //output declared as reg e_xk={r/8}; // bits divided by 8 begin if (e_xk<=4'd 2) // if e_xk is...
  9. J

    verilog problems in simulation and synthesis

    i know all the mathematics about floating point but how to represent them in verilog?
  10. J

    verilog problems in simulation and synthesis

    i am not clear about the procedure of floating point units....plz explain
  11. J

    verilog problems in simulation and synthesis

    can anyone solve the problems stated in comments in the following code.....??? module eseone(clr,e_xk1,var_xk,var_r,e_zeta_k,var_zeta_k,e_ese_xk,r); //module eseone with I/Os given in brackets input [3:0]r; //bits received by the system receiver input clr; //control signal given just...
  12. J

    When I simulate the code given below it shows clock missing!

    simulation problem i have a few questions: 1- when i simulate the code given below it shows clock missing(red lines) after certain contant intervals for the case of inp how to remove this? 2-if range of ot1 is [1023:0] and same is range for out1 then ot1<=out1; leads to serial...
  13. J

    error:HDLCompilers:217 in verilog code synthesis

    1) delays are not synthesizable...then how to wait for 2 clock cycles in each case? 2) inp is actually a buffer having a size of [1023:0] inp is to be filled by whatever bits come on s21 ,one by one on every clock edge meaning thereby that 1 bit comes from s21 and fills inp[0] on 1st posedge...
  14. J

    error:HDLCompilers:217 in verilog code synthesis

    ok...waiting.............................................................
  15. J

    DSP Algorithms implementation(I need a suggestion)

    1- auto pilot 2- controlling missile defence system
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