verilog problems in simulation and synthesis

[jameela]

can anyone solve the problems stated in comments in the following code.....???





module eseone(clr,e_xk1,var_xk,var_r,e_zeta_k,var_zeta_k,e_ese_xk,r); //module eseone with I/Os given in brackets

input [3:0]r; //bits received by the system receiver
input clr; //control signal given just once initially to clear all registers

output [3:0] var_xk,var_r,e_zeta_k,var_zeta_k,e_ese_xk; //output wires to show output,from respective registers,in simulation
output e_xk1; //output wire to show output,from respective register,in simulation

//.......................................error in systhesis..............................................................

real e_xk; //register to store result of division in decimal

//.......................................................................................................................

reg [3:0] var_xk,var_r,e_zeta_k,var_zeta_k,e_ese_xk; //outputs declared as reg
reg e_xk1; //output declared as reg

always@(r or posedge clr) //following code runs whenever bits are received by the system receiver or when reg are cleared

//........................................error in simulation..............................................................

//when clr control signal is given received r should not be wasted rather utilized when clr is 0 again

//.........................................................................................................................

begin
if (clr) //control signal to clear all registers once
begin
e_xk=0;
var_xk=1; //it should be assigned 1 initially
var_r=0;
e_zeta_k=0;
var_zeta_k=0;
e_ese_xk=0;
end
else
begin
e_xk={r/8}; //received bits divided by the number of users of system

begin
if (e_xk==0.5) // if result is equal to 0.5 output should be 0
e_xk1=0;
else if (e_xk<0.5) //if result is less than 0.5 output should be 0
e_xk1=0;

//.....................................error in simulation.................................................................

else e_xk1=1; //if result is greater than 0.5 output should be 1

//.........................................................................................................................

end

var_xk=(1-e_xk1*e_xk1); //1 minus sqaure of output gives var_xk

var_r=((var_xk+var_xk+var_xk+var_xk+var_xk+var_xk+var_xk+var_xk)+1); //var_xk added 8 times plus 1

e_zeta_k=(r-e_xk1); //received bits minus e_xk1

var_zeta_k=(var_r-var_xk); //values calculated above are subtracted

e_ese_xk=(2*((r-e_zeta_k)/var_zeta_k)); //formula to calculate e_ese_xk
end
end

endmodule

 

[user_asic]

Two things I noticed.

1. synthesis of real data type may not be supported the synthesis tool. In any case, it is probably not synthesizable, generally speaking.
2. Do NOT mix level and edge-sensitive triggers in your sensitivity list. It is not synthesizable. always@(r or posedge clr)

 

[bigdogguru]

User_ASIC is correct.

The big flaw in the design, is the use of Reals or Floats. The ability to represent these in a digital vector or parallel digital signals is limited and complex. There exists an inherit inability to represent any possible fractional part, mantissa, of a Real or Float. The sequence of bit representing the fractional part is only so long, to represent any possible fractional part the sequence would have to be infinitely long. Division in the digital world also has its inherit flaws.

You can incorporate a Floating Point Unit which would allow the use of floats in your design, however this introduces considerable complexity to the design.

Checkout this previous posting:

Discussion of Real and Floats in VHDL

 

[jameela]

i am not clear about the procedure of floating point units....plz explain

 

[RBB]

See... https://en.wikipedia.org/wiki/Floating_point

 

[jameela]

i know all the mathematics about floating point but how to represent them in verilog?