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Recent content by jakilax

  1. J

    HELP a VHDL Arithmetic and Logic Unit (ALU)

    nope, unfortunately not
  2. J

    HELP a VHDL Arithmetic and Logic Unit (ALU)

    ok, I've got it on paper now. not sure how that could possibly help me. anyways. Cheers and bye!
  3. J

    HELP a VHDL Arithmetic and Logic Unit (ALU)

    haha, why are you asking then if it's external access to the ALU or from the inside? anyways. all the code I posted is probably nonsense and might be not useful at all (that's why I didn't implement it in the first post - in order to avoid confusion). Also, in the first post I described what I...
  4. J

    HELP a VHDL Arithmetic and Logic Unit (ALU)

    external access
  5. J

    HELP a VHDL Arithmetic and Logic Unit (ALU)

    thanks for your quick response! it's very much appreciated. unfortunatelly, I honestly don't understand at all how to "realize" your hints as my knowledge in VHDL is super limited:-( could you do me a favour please and give me a code example for both?!
  6. J

    HELP a VHDL Arithmetic and Logic Unit (ALU)

    e.g. - how do I implement an immediate Read and Write Access to Acc? - how to flag the ALU for Acc = 0 (CPZ), for overflow (OVR) and for Acc = Data_Reg (AED)
  7. J

    HELP a VHDL Arithmetic and Logic Unit (ALU)

    thanks for comming back to me and sorry for being so imprecise! here is what I've done so far (I basically strugle with everything which is not implemented): library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity simple_alu is port( Clk : in std_logic; --clock signal...
  8. J

    HELP a VHDL Arithmetic and Logic Unit (ALU)

    Hey guys, I was wondering if someone could give me a hand with designing a specific ALU. Here is what I would like to implement: - sequentlial unit with 2 registers (e.g. Acc and Data_Reg) - immediate Read and Write Access to Acc - 4 funtion bits (S01 - S03) to select an OpCode (see table...
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