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Recent content by jagannathkb

  1. J

    0-1 exp vlsi job hunters in banglore

    I am Jagannatha KB did my Mtech in VLSI AND MICROELECTRONICS from NATIONAL INSTITUTE OF TECHNOLOGY CALICUT, presently working as Lecturer in BMSIT, Bangalore, I have good understanding and knowledge on digital concepts and have hands on experience of 1 year on industry standard EDA tools...
  2. J

    PhD in Digital VLSI- Help Reg

    phd in vlsi design dude try ofr iit kharagpur its good for vlsi design....
  3. J

    HOW TO REPORT AREA IN SYNOPSYS ASTRO

    HI, can any one tel me the command which will report me standard cell area, macro area, and Total cells area in ASTRO thanks jagan
  4. J

    Floorplanning question- what are the advantages?

    Re: Floorplanning question k k... dude m having problem while doing clock tree synthesis can u help me out,i havr already posted a question 3days back no 1 replied back....
  5. J

    Floorplanning question- what are the advantages?

    Re: Floorplanning question Floorplanning doesnt do anythign but CORE PLANNING, ie it will fix the core area,how we can place standard cells N all can be done in floor plan..... congestion N all taken care while routing...
  6. J

    PLZ HELP ME OUT IN CLOCK TREE SYNTHESIS==ASTRO===

    HI all, am doing my Mtech project in ASIC design, in back end design after placement when i did clock tree synthesis its not executing its showing some errors saying ===== bout_reg[0]: CP is an implicit ignore pin since is a an non-clock pin==== wat is the reason for this message N how...
  7. J

    PROBLEM WHILE ROUTING IN ASTRO

    HI all, am having problem while routing am getting some violations in ASTRO can any 1 help me out.... after auto route option am get a error messages as "Routed 52/52 SBobes, violations = 561 " i guess this error is coming from SWITCH BOX in routing...
  8. J

    .GDS FILES FOR ASTRO( FOR CREATING A MACRO LIB AND MACRO PLA

    astro gds out Dear friends I am mtech vlsi student of nit calicut. i want to design back end of my project. but In my lab there is no .gds file for ASTRO ( i need this for creating macro libraries, so that i can use it for creating macro floorplan and placement) .Please can any one send me your...
  9. J

    FLOOR PLANNING FOR MACRO NAD PLACEMENT IN ASTRO

    macro placement + floor planning guys, can any one tel me the steps how to floorplan for MACRO,i e we have to keep separate space for macro and place MACRO in that space.[/b]
  10. J

    AM getting some warning message in the code

    ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:05:52 10/26/2008 -- Design Name: -- Module Name: vector2int - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- --...
  11. J

    Need vhdl code for BYTE PERMUTATION for AES

    I have problem in implementing the vhdl code for byte permutaion i,e 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 byte permutaion is we have to keep first row same 01 02 03 04 second row has to shifted by one byte left i,e 06 07 08 05 third row by two left shift 11...
  12. J

    Problem in implementing Advanced encryption standard core SBOX

    any one help me out have problem in implementing Advanced encryption standard core SBOX, i need a vhdl code for SBOX ================================ type type_SBOX is array (0 to 255) of std_logic_vector(7 downto 0); constant c_SBOX_FRV : type_SBOX :=...
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