AM getting some warning message in the code

[jagannathkb]

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:05:52 10/26/2008
-- Design Name:
-- Module Name: vector2int - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rconnn is
port (a : in std_logic_vector(3 downto 0);
bout ut std_logic_vector(7 downto 0);

rst:in std_logic;
clk:in std_logic);
end rconnn;

architecture Behavioral of rconnn is
--signal b: integer;
function mvl2int(opd:std_logic_vector(3 downto 0)) return integer is
variable temp:NATURAL:=0;
variable j:NATURAL := opd'length-1;
begin

for m3 in opd'range loop
if opd(m3)='1' then
temp := temp+2**j;
end if;
j:= j-1;
end loop;
return temp;
end mvl2int;


type type_RCON is array (0 to 9) of std_logic_vector(7 downto 0);
constant c_RCON : type_RCON := (x"01", x"02", x"04", x"08", x"10", x"20", x"40", x"80", x"1B", x"36");

begin

process(clk,rst,a)
variable romvalue:std_logic_vector(7 downto 0);

variable temp1:integer;

begin
if (rst='1') then bout<="00000000";

elsif(clk' event and clk='1' )then

temp1:=mvl2int(a);
--b<=temp1;

romvalue :=c_RCON(temp1);
bout<= romvalue;
end if;
end process;
end Behavioral;

this is program which converts given hex number to integer N gives the look up table output, this is small block in AES design....

because of that waring message am getting some error when i excute in DESIGN COMPLIER , so anyone can tel me wat exactly the problem, hope u ll slove it