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Dear Sir,
I tried to perform a LTE tranceiver simulation of a GaAs PA MMIC. I use foundry’s pdk.
I simulate hamonic balence of the MMIC circuit. It’s OK.
Then I change the src to LTE-FDD-DL-testmodel，and change the relevant sink.
The LTE simulation testbench is similar to the example of...
How to relink ADE state of Virtuoso?
I have a vituoso project. Many ADE simulation states are stored in ~/.artist_states directory.
Today, when I launch virtuoso ADE, all these states disapear. I turned to ~/.artist_states directory.
I find that all the states directories are still there, while...
How to post-sim by a PEX extracted netlist?
I managed to run PEX. Parasitic netlist named *.PEX.netlist is generated. However, maybe due to some inevitable problem from pdk, there exist lvs error. Maybe as a consequence, the Calibre View could not be generated.
My question is, how to perform...
RVE couldn’t start after PEX Calibre
I run Calibre PEX. There exist some lvs errors.
After that, I tried to start RVE. However, the RVE view emerges for several seconds then disappear. The error message is:
It seems that top cellview missing. However, there exist the top cell in this library...
Dear,
I try to simulate HB of a foundri’es nmos. Everything seams OK except a warning of:
After sim, I launch plot MainFrame and select HB as following. I wanna plot Gain vs Pin. I was then stopped by selecting ”mumerator output instance terminal”. I tried to click everthing in schematic, but...
Dear，
I need to design a GaAs Willkinson divider. I found the phase and amplitude abrupt change in 2GHz or so. The layout is simulated by ADS momentum.
Is it produced by the ring resonation of Willkinson divider structure?
Are there anybody else encounters this problem?
How to avoid the...
see the example of ADS layout momentum simulation. The 50oHm GND is implied.
sometimes you need to get back to schematic and load the layout for simulation.
How to build up nonlinear model of a FET in Foundry pdk?
I use ADS.
I meant to research some FET nonlinear parameters variation with Foundry process and design , such as Cgs and Cgd. I have pdk of the Foundry, and I can find the FET nonlinear large signal model.
Would you plz tell me how to...
How to extract Voltage of a schematic net?
I use ADS.
I need to extract voltage of schematic circuit. I can find I_probe and P_probe tools. They work fine. While I can’t extract voltage of a circuit net via V_probe tool. Plz help me.
Jade
Dear,
I use ADS. I am quiet puzzling about the definition of Z-matrix and Zin and Zout.
Question:
In ADS, I use stoz(S) to get the Z-matrix of the network.
In schematic, I write the following measurement equations to get Zin and Zout.
Ztmp = stoz(S, 50)
RinEVB = real(Ztmp(1,1))*50
XinEVB =...
Dear Sir,
Manipulation of S-parameters from a dataset and re-assemblying them to a new dataset.
I just want to realize such effect:
1, load a dataset from DAC.
2, Extract S-parameters from the dataset.
3, Do some manipulations to each element of the S-parameters. Such as conjugate.
4...
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