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Recent content by izye

  1. izye

    Looking for resources about ESD layout

    Hi all, I would like to know more about esd layout. Could you give any input and where to find more information or tutorial about this. Thanks Added after 30 minutes: I need more info on layout..books?website? anyone..can help me pls... thanks..
  2. izye

    Dose Analog IC Design & Layout have a good future?

    yeah..for me its not just polygon..when you come to the top cell, it will be more challenging.. Layout designer is in need today..You can have a good future... And also try circuit design if you want more more n more challenging work..
  3. izye

    Why LVS is showing that two nets are shorted while they are not?

    Re: doubt in LVS I think If the outer connection is right, there must be short in the substrate or any missing contact. The connection should be check carefully.Sometimes we did'nt realize small mistake. I agree with psmon, you should check wheter you have check the "join in same net" while do...
  4. izye

    Matching Pair for layout design

    thanks jerryzhao, thanks srieda.. Actually the circuit is done initially in order to get high gain op amp . The simulation was okay...However, while doing the layout, I realize there are some mistake/or not.. However..thanks..maybe I understand a little bit here
  5. izye

    Matching Pair for layout design

    Yup..why you said that the bias circuit like that cann't supply good current source. You means if the transistor have the same length, but different width is okay to apply in the layout design?
  6. izye

    Matching Pair for layout design

    Hi, For the matching pair in Layout design, I am confused about their size for MN0, MN1 and MN5. Supposed that the matching pair should be in the same size right in the layout design? If their not in the same size, are this design wrong? Thanks all...
  7. izye

    Questions about poly layer in CMOS layout

    Re: CMOS layout? For question 1: I think you better used metal to connect poly because poly give much much higher resitance. Transistor gate in analog design very sensitive and preferable to connect it with metal.
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