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Recent content by itacool

  1. I

    Modeling VCO load effect on PLL settling

    Do you mean that (f2-f1)/Kvco is the voltage step in tuning voltage of the VCO ? (has unit of volts,not rad) Thanks
  2. I

    Modeling VCO load effect on PLL settling

    Hello and thanks for all replies. I meant linear system as assuming the loop is near locking and can be modeled using phase variables. The perturbation is small that the loop is still stable. Let say the load is changing from Z1 to Z2, how to model it in the phase variables. I thought also that...
  3. I

    Modeling VCO load effect on PLL settling

    Hi, The VCO is a cross coupled LC . The PLL loop may not lose locking, but i want to calculate the transient behavior till settling. The load is abruptly change (like step response). Thanks
  4. I

    Modeling VCO load effect on PLL settling

    Hello, I have a PLL where the VCO's load is abruptly changing. I want to model the load variation as a small perturbation assuming linear system for calculating the loop response. any book chapter/paper deals with that? Thanks
  5. I

    [SOLVED] "only one connection" while simulating av_extracted

    Hello, I'm trying to run dc and ac simulation for my layout,using Cadence and TSMC65. The output performance are poor, and i'm not sure it's because a bad design, or simulating problem. while running the simulation, the following warnings pops on the spectre.out file: Notice from spectre...
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