Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi. I am working at Analog IC Design.
I still trying to view Histogram graph with Monte Carlo Results(mt0, ma0, ms0) by Sandwork SpiceExploer.
Please help to me?
It is a good document!
I can have a clear conception of Poles and Zeros...
Thank you.
P.S.
Book : The Scientist & Engineer's Guide to Digital Signal Processing
https://www.analog.com/processors/learning/training/dsp_book_index.html
Generally, OTA Topology is like as Diff-Amp's
Av = B gm Ro
If you want to observe the output current,
It can be measured between PMOS and NMOS at output node.
I(OUTPUT) = I(PMOS)-I(NMOS)
Regards,
iPierre
Re: How to simulate unit-gain-buffer use gain-boosting in Hs
Generally, in order to reduce Vdsat,
the size of any transistor should be as large as possible.
Vdsat =( 2Id / Kp*(W/L) )^(1/2)
and, adding one-stage(rail to rail) in your amplifier may be recommended.
Regards,
iPierre
P.S...
Re: How to simulate unit-gain-buffer use gain-boosting in Hs
Please check M6, M8 Trs. in saturation,
and reduce Vdsat under each 0.2v.
Because, 0.4v loss is two Vdsats from OUT 1.4v
I am designing DC Circuits, have a question as below.
Please see the attached file.
Why to use NMOS connection? I know it can connect VBL directly without NMOS tr.
i am not sure is it good, and whether there was any concern.
Best regards,
iPierre
Re: corners
Comparison of twos as below.
Red ss -40 <-> Beige ss +125
Blue ff -40 <-> Green ff +125
Red ss -40 <-> Blue ff -40
Beige ss +125 <-> Green ff +125
Left's Vth is larger than Right's. so then Each vout levels are inversly regulated.
Analysis showed that it consisted...
Re: problem about ldo
Here is a good reference of LDO regulator.
"Current Efficient, Low Voltage, Low Drop-out Regulators"
by Gabriel Alfonso Rincon-Mora (Freely download)
Regards
Re: corners
I think so that short-length MOSFET has a great influence on Vth Variation.
When VDD increasing, |Vth| be reduced by short-MOSFET effect.
Please check to simulate it by using 1um instead of 0.35um
and, plz show vin+, vin- signals.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
