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I am using 0.35um process.
I have also considered many other Schmitt triggers, but each has its own strength and weakness.
I have been receiving different answers on how to calculate its minimum VDD.
Some suggest it is: 4VDS
While others say it is: 2Vth+1VDS
Mentioned in most text, the circuit shown below is not suitable for low-voltage applications.
If I am not mistaken, this mean it is not suitable if VDD is low. correct?
How do I calculate the minimum VDD required for this schmitt trigger?
temperature sensor
I remember making a temperature sensor for my final year project using PIC, but not the detail.
I found some reference material that may be helpful to you:
https://www.electronic-circuits-diagrams.com/sensorsimages/sensorsckt9.shtml
https://quozl.linux.org.au/ts/
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Hi,
Has anyone heard about Wafer-Level Cameras (WLC)?
https://www.semiconductor.net/article/CA6634202.html
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My question is, how zoom/autofocus function are controlled?
Previously a motor, driven by a motor driver is needed. Does it mean that with this new technology...
Re: Capacitive Load
Nora,
Yes a piezo buzzer is also capacitive.
This link contains some information on piezo buzzer:
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If you do a quick search on the net, you will find that specs of piezo buzzer contains the capacitance of the buzzer.
finding capacitive load
On the gate of the MOSFET is an oxide layer separating the metal layer and semiconductor layer hence the name MOS.
Ideally the oxide layer is an insulator, but there is a very minute current leakage through it (nA/pA). Therefore it can be said that the input resistance...
how to determine pin is high impedance
GZ does not necessary be between Vdd -Vss depending on your circuit topology.
Try connecting pull up and pull down resistor at your output and measure the output voltage.
High impedance state may just be for the output path of the I/O pin. The output of...
typical high impedance values
In a high impedance state the value would generally be undetermined.
Example: If you are using a CMOS inverter and both the NMOS and PMOS are off, then the output can be anywhere from Vdd to Vss.
If you were to connect a pull up and pull down resistor (of equal...
Is it possible to design an I/O buffer with supply voltages 3V-5V but input signal of 1.6V-2.3V.
The aim I hope to achieve is to use only MOS and input threshold voltage having hysterisis of >0.2V.
Any ideas???
pc power supply
You can use a DC-DC converter, example:
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OR MVR like that used in automobiles:
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Parasitic diode is because a MOSFET does not have a PN junction. The parasitic acts almosts like a normal diode in a MOSFET process.
It is espeacially usefull in a bandgap circuit.
Hope this is what you wanted to know.
capacitive kickback
I agree with pinoy.
Infact, the capacitor can be used to absorb the voltage spike.
If the voltage across the capacitor is removed, it will slowly discharge. This will not cause a voltage spike.
Input rail to rail means that it the input voltage can approch both supply voltage before going to an unknow state.
Output rail to rail means that the ouput is able provide a maximum voltage of VDD and VSS.
Previous Discussions on EDA board:
for more detials view:
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Look at:
There is a book posted on that dicussion. It may help you.
Voltage References: From Diodes to Precision High-Order Bandgap Circuits
by Gabriel Alfonso Rincon-Mora
Wiley-IEEE Press; 1st edition, October 2001; 192 pages
ISBN: 0471143367
scanned pdf
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