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Recent content by Indrajit Ghosh

  1. I

    Operating System question?

    Computer organization question? Which one occupies 1/4 of the main memory of the computer? 1. User program 2. Priority program 3. Operating system 4. Compiler & interpreter?
  2. I

    verilog code regarding sequencing of instantiation help!!

    so if there is no trisate, then how will i make a input port not to accept any values ? And does simulation support tristate?
  3. I

    verilog code regarding sequencing of instantiation help!!

    as now you can see,since you pin pointed out where I am going wrong I am able to correct myself....and to tell you the truth I have started learning hdl by "myself" about a month or so without any "teacher" or whatsoever .....so it is obvious i may start out with writing broken code,ask stupid...
  4. I

    verilog code regarding sequencing of instantiation help!!

    I tried to design a mux, to make a data communication path between p1_p2_new_calc ans sinr ,the code is having some problem help me out..... module control_unit(p1,p2,clk,si,cs_si,cs_p1,op_nd_p12_in,op_si_in); output reg [63:0] p1,p2,si; input clk; output reg cs_si,cs_p1; //reg cs_reg...
  5. I

    verilog code regarding sequencing of instantiation help!!

    it would had been helpful of at least giving solutions or idea on how to go about this specific problem rather than giving HDL philosophy....
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    verilog code regarding sequencing of instantiation help!!

    p1_p2_initial_calc c1(.p_max(p_max),.p1_ini(w1),.p2_ini(w2),.clk(clk),.cs(cs),.rdy(cs_pi)); SINR_PU_CALCULATOR c3(.p1(p1),.p2(p2),.si(si_c),.clk(clk),.cs(cs_si),.rdy(high)); p1_p2_new_calc c2(.si(si_c),.p1_n(z1),.p2_n(z2 ),.cs(cs_p1_p2),.clk(clk),.rdy3(ok)); now I have three...
  7. I

    how to sequence ipcore?

    The ip core i am working with is this one.... https://www.xilinx.com/support/documentation/ip_documentation/floating_point_ds335.pdf
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    how to sequence ipcore?

    if suppose the ready signal of an ipcore goes high after a valid result ,and if i want to make the ipcore evaluate multiple times will i have to clear the ready signal using the sclr (synchronous clear) control signal or will it be cleared automatically when new operands will be evaluated...
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    how to sequence ipcore?

    what I want to achieve is that I have two cores p1 and p2 whose instantiation template is as sub p1 (.output(Y),.a(A),.b(B),.clk(clk)); add p2 (.output(Z),.a(Y),.b(C),.clk(clk)); now as you can see the second core uses the output signal of the first core.....now when core p1 evaluates it...
  10. I

    confusion in disabling a signal in verilog!!

    how to know whether the code forms a latch or not? since the synthesizer is not showing any warnings nor any error!
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    confusion in disabling a signal in verilog!!

    module Ui_UPDATION_CALCULATOR(si,clk,rst,cs,ui_new); input [63:0] si; output reg [63:0] ui_new; input clk,rst,cs; parameter ct=64'b0011111110111001100110011001100110011001100110011001100110011010;//ct=.1 parameter...
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    question regarding execution of instantiation in verilog!

    so basically you mean to say ,If i instantiate the same ipcore even 10 times ,it will be treated as separate piece of hardware working independtly,so even in the rtl description will it show as separate pieces of hardware?
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    question regarding execution of instantiation in verilog!

    Will there be any signal contention if i try to instantiate the same ipcore simultaneously from two different modules?
  14. I

    question regarding execution of instantiation in verilog!

    I am a bit confused about the order of execution of Instantiation of modules, suppose i instantiate 5 modules one after the other , now will the instantiation will be done sequentially or concurrently? What will be the behavior if A> The instantiated modules are interdependent ? B>The...
  15. I

    confusion in disabling a signal in verilog!!

    ok thanks i will see to it...
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