#### Indrajit Ghosh

##### Junior Member level 2

Code:

```
p1_p2_initial_calc c1(.p_max(p_max),.p1_ini(w1),.p2_ini(w2),.clk(clk),.cs(cs),.rdy(cs_pi));
SINR_PU_CALCULATOR c3(.p1(p1),.p2(p2),.si(si_c),.clk(clk),.cs(cs_si),.rdy(high));
p1_p2_new_calc c2(.si(si_c),.p1_n(z1),.p2_n(z2 ),.cs(cs_p1_p2),.clk(clk),.rdy3(ok));
```

now I have three instantiations as you can see, what i want to do is to make a control unit which will do the following jobs

1>initially p1,p2 of sinr should be the signals w1,w2 respectively (where p1,p2 are input to sinr,and w1,w2 are output)

2> after that p1,p2 of sinr should be z1,z2 of p1_p2_new_cal..,

3>after that only signal exchange between sinr and p1_p2_new_cal should happen when sinr is enabled p1_p2_new should be

disabled and vice-versa ALSO (p1_p2_initial permanently disabled)

here cs=control signal i,e the instantiation will only work if cs=high and rdy is the ready signal i.e it will generate a high signal when the output of that instantiation is ready.

help me out to write it in verilog!