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Recent content by Indrajit Das

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    Measuring transfer characteristics of fully differential OTA

    Hi experts, It would of great help if you could suggest a good reference manual to experimentally measure the open loop gain and phase response of a fully differential two-stage OTA. I have access to required instruments like voltage supply, signal source and a CRO. Thanks, Indrajit
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    conversion gain of a N-path mixer

    Hi all, Can anyone suggest what will be the conversion gain of a N-path mixer (say, 4-path) as compared to the conversion gain of a single-path current driven mixer? What will be difference in the two conversion gains? Thanks in advance. Indrajit
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    Capacitor Mismatch Coefficient for gpdk 180nm technology

    Thanx erikl, littlej_zju....for the reply. Got the point. I understand the point that these statistical data varies from foundry to foundry. So, its difficult to have any kind of genralized theory out of it. May be I would find relevant papers in the literature. Regards, Indrajit
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    Mismatch model files required for umc 180 nm process

    Ok thanx man
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    Capacitor Mismatch Coefficient for gpdk 180nm technology

    Hi erikl, Yes, I got ur point. But, regarding this I would like to ask something. Actually my prof has asked me to show some kind of analysis of the capacitor mismatch that occurs in a real fab scenario in my interim progress report. For that, I am doing various kinds of research over the...
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    Capacitor Mismatch Coefficient for gpdk 180nm technology

    Hi erikl, Thanx for the reply. But, can you please tell me, the data provided by you is of which foundary? And can I get the full document, ie the source file, I would like to have detailed understanding of the topic. Indrajit
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    Mismatch model files required for umc 180 nm process

    Hi, Can anyone share with me mismatch models for umc 180nm mixed mode, regular vt process. Or, at least if anyone could tell where or how to generate or find (in case it is already included in the umc package), that would be of great help. In this regard, I would like to mention that I am...
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    Possible solutions to Input parasitic capacitance problem

    Hi experts, I am designing a SAR ADC in gpdk 180 nm technology. Now, I have designed all the sub-blocks of a SAR ADC like comparator, SAR logic etc. Now, the problem that I am facing is that the DACout voltage is not settling to exact voltage values that they are supposed to during the clock on...
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    Capacitor Mismatch Coefficient for gpdk 180nm technology

    Hi experts, I am designing a 8 bit CDAC for the SAR ADC that I want to design for my masters project. Regarding this, I want to know about mismatch coefficient of capacitors (Ac) for gpdk 180 nm tech. because, using the mismatch concept I can decide on the LSB cap value that I need to use...
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    Problem in creating logic to electrical connect module in verilogams in Cadence ADE

    Hi, I am trying to make a logic to electrical connect module that can convert logic ( '1' or '0') at the input side to electrical pulses at the output side, implementing in verilog-ams, its required for one of the project that I am doing. But, the problem that I am having is that, its running...
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    Problem in creating logic to electrical connect module in verilogams in Cadence ADE

    Hi, I am trying to make a logic to electrical connect module that can convert logic ( '1' or '0') at the input side to electrical pulses at the output side, implementing in verilog-ams, its required for one of the project that I am doing. But, the problem that I am having is that, its running...
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    Designing FIR Filter using Cadence Tools

    Hello everyone, I am required to design FIR filter using Cadence tools for one of the projects that I am currently doing. I would like to mention that I am very new to this and have never done filter designing in cadence. Even have very minimal experience in Filter design in MATLAB. Thats why...
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