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Recent content by imbichie

  1. imbichie

    [SOLVED] How to do debug a design post implementation in fpga

    What FPGA you are using, if its Xilinx FPGA, you can use the ChipScope to debug the signals in your design...
  2. imbichie

    Priority based Place and Route in FPGA

    Hi All, Thank you for your time and replay. @dpaul : Now I am using Vivado 2014.4, but I have the flexibility to choose any vivado version with license, if the other higher version of vivado solves my issue. @pbernardi : I already checked the UG903 constraint guide before I starting the...
  3. imbichie

    Priority based Place and Route in FPGA

    Hi All, I am using Xilinx Kintex 6 Ultra-Scale FPGA for my design. Synplify Premier for Synthesis and Vivado for PnR. My fpga utilization is more than 93%. I am facing some critical timing violations in one of my module. Is it possible to do a priority based place and route, so I can give the...
  4. imbichie

    Inferring DSP blocks in Synplify Premier using SDC Constraints

    Hi All, I am using Virtex 7 1157 FPGA. My design with RTL is freezes. I cannot modify a single line in the RTL. I needs to infer the DSP blocks for particular adder logic in my design. During the Synplify synthesis, I observed that automatically these adder are not using DSP blocks. Is there...
  5. imbichie

    Master and slave address relationship in the AXI4LITE

    This can achieve if your Master Slave interconnect (AXI Interconnect Bridge) design supports it.
  6. imbichie

    How to avoid negative interconnect delays in SDF generation ?

    Hi All, Please let me know, how the negative interconnect delays are coming in SDF file, even though for a long wire length net (almost 1030 um) ?
  7. imbichie

    AMBA AHB address question

    In AHB, a single address like , 0X00, 0x01, 0x02, etc is used for addressing a Byte. If the Data Width is 32, which means there are 4 Bytes, so if the address of the current burst is 0x30, then the address of the next burst will be 0x34.
  8. imbichie

    [MOVED] Virelog code having problem while getting output

    Re: Virelog code having problem while getting output I think inside the always@ clocked process statement you need to use the "<=" operator instead of "=" operator Is the simulator showing any error or warnings ? What is the given inputs and expected output ?
  9. imbichie

    Test the Setup and Hold time of a SRAM memory

    Hi All, I am using some memories in our design. I got the setup and Hold time values of the memory from its *.lib file. But I need to test (Not only in simulation but as well as on real chip) whether the values are correct or not. Is there any way to (either standard or other) test the Setup...
  10. imbichie

    Image and Video processing implementation in FPGA

    https://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/ReferenceDesigns/ReferenceDesigns01/71LVDSVideoInterface.aspx This may help you
  11. imbichie

    why this error happen?

    "wait" statement cannot be synthesis ...
  12. imbichie

    Alarm clock verilog code cannot compile

    Hi, The code in the #1 post have an extra end at line number 493 its not needed. Also i don't know why you are giving input/output declarations for the non-port internal signals from line numbers 12 to 40 in the code in #1 post. You can declare these internal signals as either wire/reg.
  13. imbichie

    Differential Clock - why?

    There are several advantages to using differential signaling. Three of the most important are these: (1) Differential receivers reject common mode noise due to skew, power supply noise, interference, etc. (2) Differential signals effectively double the voltage swing at the differential...
  14. imbichie

    [SOLVED] convering fuction in vhdl

    You have to give signed argument for the conversion I think this may solve the error in1_int <= conv_integer(signed(in1)); But I think instead of conv_integer you have to use the to_integer function please see the below link http://www.xilinx.com/support/answers/45213.html
  15. imbichie

    Any free FPGA physical Layout tool outthere?

    Which FPGA you are using ? Each FPGA vendor have their own FPGA tools... If you want a to do upto synthesis, then you can use the Synopsis Synplify Pro or Premier.
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