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Recent content by Ikon

  1. I

    set up and hold time, transisitor level - explanation needed

    Good book. Thanks a lot for adding it here. I am able to download it
  2. I

    verilog code for 32 bit multiplier

    verilog code for multiplier Hi All, I am in need of a verilog code for a 32-bit multiplier. i have searched in sourceforge.net but did not find the verilog code for 32 bit multiplier. If any one of you has the code, please upload it. Kind Regards
  3. I

    HIGH FREQUENCY CMOS DESIGN STYLES TEXT

    Hi I have downloaded the same book from rapidshare. It is asking for password. If any one has it, kindly share it with me. Thanks...
  4. I

    Needed this Book. "High Speed CMOS Design Styles".

    Hi I am in need of this book"Kerry Bernstein & et. al., High Speed CMOS Design Styles" If any one has it , please upload it. Kind Regards
  5. I

    Wanted to know about Reverse Body Bias

    Hi Friends I Wanted to know about Reverse Body Bias (RBB) and its operation. Cheers
  6. I

    Looking for "Leakage in nanometer CMOS technologies" book

    Hi Friends I am in need of this book, If any one has it please upload it. "LEAKAGE IN NANOMETER CMOS TECHNOLOGIES" ( Edited by Siva G. Narendra and Anantha Chandrakasan ) Cheers.
  7. I

    working of SOC Encounter

    Mr P.Shinde, Go thru the docs provided with the tool,if u want to know about the tool need to do some research on it, then u will know more points. So plz go thru the docs, search the net u will find a lot. Thanks
  8. I

    Inbuilt tools in Soc Encounter

    Hi , C SOC-ENCOUNTER is not a tool but a PLATFORM. As u mentioned it has PKS ( Physically Kowledgable Synthesis Tool) this is used to do a initial floorplanning ,power planning and trial routing, so that at the time of synthesis u have a rough detail about ur interconnect and the area ur...
  9. I

    Globat net connections in encounter

    Hi, Consider u were given a block to do. For the u need to have Main VDD and VSS lines around it, and thru these ur standard cells get the power connections. In the encounter u use global connections for these. Hope this helps. Thanks
  10. I

    how to import gds2 file into virtuoso layout editor

    virtuoso stream form Hi Go to the CIW Window, In the FILE MEMU u have IMPORT AND EXPORT commands open it, select STREAM, window gets displayed, and there u will have the details u have ti fill in. Hope this helps bye
  11. I

    connect VDD pad to power ring

    Hi, If u have a process document just refer that, there u have these values. The notmal Metal width used inside the std cells shud not be used here and the width of the metal lines that are used to connect to PAD and Power rings are usually higher. I am sure that these values are present in...
  12. I

    substrate or well contact

    Hi, In CMOS we come across "LATCH-UP" . If this occurs then our ckt /transistor fails. In order to avoid this latch up, the layout engineers use Substarte and well contacts.
  13. I

    Sizes of mos in flip-flop and transmission gate

    Hi, For the Transmission gates we use the minumum width of NMOS and PMOS. I have no idea for the flip-flops.
  14. I

    calculate width for power ring

    Hi, The width of the power ring depends upon the power consumption of the Block (or chip). For Eg : If the power consumption of a block is say 300mw , then divide it into 4 parts. we get 75 mw on each side. based on this assumption we go ahead and calculate the width of the power lines...
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    Clock Tree Synthesis - CTS

    Hi , I have a question regarding Clock Tree Synthesis. I have a design, and I need to run CTS on the design. 1. How do I decide on the number of levels of buffers required for the clock tree? either it is 0 level or 1 level or 2 levels ? thanx
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