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Ya, you are right!
Especially here, you never konw what the weather will like next minute.
I even told my parents on QQ, that it was sunny outside maybe I could meet Cynthia later, when they were enjoying mooncakes and moonlights.
BYW, I'm a little missing the only one mooncake in my stomach...
Hi, Brittany Snow!
After watching the The evening party of Mid-Autumn Festival(CNTV ZhongHuaQing) on website, Cow, What a beautiful cloudy night!
CLOUDY!!! YouMuYouA(phonetic transcriptions of Chinese characters)!!!
hi，jagadeesh_006 ！
I am wandering why u have to do so?
How can DC pick up a STD cell for the "input path" whose delay time is less than 0, since (period - input_delay) is a negtive value.
Hi qual_ti!
I am wondering where ur physical and circuit came from?
I've achieved aproject that some non clock cell in the clock path, but It is a very slow project (clk period = 9ms), and there's no timing violation during STA.
Normally, we can not add non clock cell into the clk path during...
Hi, ee1!
Normally, we put a series of verilog files which related to each other in a folder, just read in all of them.
And sometimes we can find the relationship between verilog files in file head.
I have no idea about how to read in all the interrelated verilog files for different projects...
Hi there!
1.We set false path, course we want to tell tools don't care about these special path, and we can make sure these defined path have no need to check or we have other methods to check. STA tools will analyze every possible path, if we dont ask them not to do. So we have to analyze...
Hi rayhuangno!
U dont need to edit it, just delete it.
U can copy it to ur own project directory, then u will able to edit it.
The setup files in ur project directory has the highest authority, they will overwrite other setup files.
Best regards!
Hi there!
In the Cadence CDB database, each cellView is accompanied by a pc.db text file that lists the library, cell, and view name of each cell instantiated within the cellView. CAD developers use this file to quickly determine the dependency graph of the design, without opening any...
Hi alirez.m.f
Do U mean how to transfer a synopsys format lib to cadence format? especially for the backend libs.
U r right, LC can only compile lib to db. It can also deal with edif, but not for backend libs.
Libs are supplied by lib venders, both cadence and synopsys format files...
Hi niladri.s.debnath!
It is definitely true that VCS will check setup time and hold time if SDF is annotated and "-notimingcheck" is not used.I've glanced the VCS cmds this morning.
I'm sure, basically, Suppose some violations exist, VCS will give out a waring about them. such as violation...
Hi niladri.s.debnath!
R u sure ur critical path is not a false path?
To my knowledge, we dont need any particular cmd for setup time check.
VCS will do it automatically if the sdf is annotated correctlly.
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