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Recent content by ianalog

  1. I

    SOC encounter PAD.io file

    hello, everyone. who have a pad.io file of encounter. Please upload to me . Thank you very much!!! ianalog
  2. I

    DC error: Syntax error at or near token 'enum_state'

    when using DC, the error is shown , Syntax error at or near token 'enum_state', the wire is set as ---reg [4:0] cstate ; why is error? please help me. thank you .
  3. I

    How to add IO port by NEW-DC?

    in encounter, some specific file is what? how to get this file? the IO.ioc file is the file? I feel that the io.ioc file only set pin, not set pad and frame. is it ?
  4. I

    Generate netlist from layout!!

    first, you must have the extract LIB . then, you may extract the netlist by diva or calibre. From the extracted layout we may get the netlist.
  5. I

    How to add IO port by NEW-DC?

    now , DC has obsoleted some command, FE. set_port_is_pad, insert pad and so on. however, how to do the auto-IO P.P. by SOC encounter? is there other new command to use ? thank u
  6. I

    Can't see ACTIVE, NWELL, NSD nor PSD in GDS file of 0.18 based layout

    018u layout question I have copy the display file, dont know why? Added after 6 minutes: down load sample file can see all layer, but the std_lib file can not be seen all layer. why?
  7. I

    Can't see ACTIVE, NWELL, NSD nor PSD in GDS file of 0.18 based layout

    hello, everyone. I designing a layout based on 0.18u, the PP tool is SOC encounter. when i open the GDS file with virtuoso, I don't see the ACTIVE, NWELL, NSD and PSD. would you tell me is it correct ? thank you !
  8. I

    hello, in where is there this fpga board, thanks.

    Iouri, thank you very much! ianalog
  9. I

    hello, in where is there this fpga board, thanks.

    the fpga board with TFT_LCD , please tell me. thank you.
  10. I

    Looking for DivaEXT.rul file for netlist extract

    Hello ,anyone I am a fresher in analog IC. I need a divaEXT.rul file for my netlist extract including the resistor, capacitor and CMOS and so on. thank you for sharing you experience!
  11. I

    Where to get SDC files?

    SDC sources you may use a commant as write_sdf *.sdf in the Design_vision.
  12. I

    How to do LVS in Virtuoso only with layout?

    LVS in virtuoso you can extracte the layout and get a netlist, then , you can verify it with hspice .
  13. I

    post-layout simulation +sdf_annotate

    sdf_annotate verilog Thank you , aslijia and aji_vlsi. write_sdf -v 1.0 ***** sorry, I dont understand what it mean? I didnot use this command. please tell all of . I check my log. the log file give a message of timing violation. Warning! Timing violation $hold( negedge XC &&&...
  14. I

    simulation with SDF uing model sim

    modelsim sdf annotation I met the same question. Modelsim simulator donot support. when I use the NC-verilog, it is OK.
  15. I

    post-layout simulation +sdf_annotate

    sdf_annotate HI,all, Now I would like to run a post-layout simulation with sdf file back-annotated. I add the sdf file into my final gate level netlist (by astro) and using the NC-verilog simulator. The tool of plant and route is the Astro. I got the simulation result of gate-level netlist of...
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