Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I was trying to simulate crystal oscillator (with square wave output)'s phase noise. Usually what number of harmonics do you use in a harmonic balance simulator to get a realistic results?
Hi,
I've seen a lot of topics about ESD protection on CMOS I/O pads. But I wonder, how do source follower type of output pad get ESD proctection?
For example, how do you ESD protect an LDO's output pad? Does the source follower device has to be laid out using ESD layout rules?(such as wide...
post layout bandgap
but the question is, the extracted netlist from layout contains the area parameters and the post layout simulation is way off.
If I remove those "area" parameters from the extracted netlist, the results are good.
So, do you mean that the extracting software did a wrong...
Hi,
I have a question about BJT in CMOS process.
let's say, the foundry supplies model PNP18A100 for a 10ux10u BJT,
when i use it, do i need to put area parameter in the spice line?
such as,
Q1 1 2 3 pnp12a100 AREA=1e-10
or do i just use
Q1 1 2 3 pnp12a100
...
why sandwich cap is preferred?
from this paper:
Capacity Limits and Matching Properties of Integrated Capacitors
By Roberto Aparicio, Ali Hajimiri,
The sandwich caps made by interconnect metals don't match well.
In the fab's matching report, only finger(comb like) caps are used. and the...
Thanks for the reply!
what is fringer cap? is it also called comb cap?
How's the matching of such caps? is there a layout pic of such caps?
how about sandwich caps, is it good or bad?
Thanks!
why are they called sandwich caps?
Hi,
Has any one designed analog ckts in pure digital logic process? How do you handle the capacitor matching?
if there is no MIM or PIP available, what kind of caps do you use? How about using the interconnect layers? is the matching good for a 10bit...
Hi,
I am playing with a 0.13um fab model right now. my question is , how can I set up a circuit to calculate the gamma in the MOS thermal noise formula
in the text books, gamma is 2/3 for long channels, but they say gamma can go higher in short channels, even as high as 2.5 in Razavi's...
in Razavi's Book P408 figure 12.4
He said, when hold clock rises, S1, S2 off, S3 on, Vout will be Vin*(C1/C2)
I did some simulation, set C1=C2=1pf, and found out Vout was 0 and VB=-0.3v (vin=0.6v)
what was wrong in my HSPICE code?
*Razavi P408 Fig 12.4
* Used to test ideal Sample and...
I found that in many pipeline ADC designs, a S/H stage is included (vin-->S/H-->stage 1-->stage 2...), however, in other designs, S/H was included in the 1st stage. (vin-->stage1-->stage2...)
What are the pros and cons about having a dedicated S/H stage?
Thanks!
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
