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Recent content by hyena_dale

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    How to make a complete plan to verify a mcu?

    Re: how to verify a mcu We use C model to verify core except peripherals. For golden C model, design a golden C model is more easy than design a golden RTL. For C model verification. First, you can compare C code with spec, check software is easy than check RTL. Second, U can verify your C...
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    Issues with DC and RTI files with include construct

    Re: DC issue Maybe you can try your scripts like this : read_verilog {include.v main.v}; I just used this method in combine multifiles.
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    How to make a complete plan to verify a mcu?

    Re: how to verify a mcu the one of our way is to write a C model, compare result cycle by cyle.
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    Do we need to read the sdf to do STA after P&R ?

    primetime read_sdf pdf Of course. SDF from backend tools include accurate timing delay information.
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    STA problem need help!

    setup time = clock cycle - max data delay hold time = max clock delay(skew) - min data delay With worst case condition, setup time can get most critical value, With best case condition, hold time can get most critical value in mostly environment.
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    Question - clock skew in PrimeTime

    You can read a sdf file from backend tools, then use "report_clock_timing -type skew -clock clkname -verbose"
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    typos in intel's pc sdram spec.?

    Sdr exit from refresh depend on CKE only. However, it must stay at IDLE status after exit refresh, so, CS# must stay at high.
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    nanosim integrated with VCS problem

    I never meet this problem in Nanosim-Vcs cosimulation. Maybe you need to set "VCS_HOME" variable in your environment.
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    Cadence IC 5033 on Solaris 10 (x86)

    Sun has a project named "Janus", this project can let linux application run on the Solaris X86. However, this project was postponed. So, the first release of Solaris 10 (X86) isn't include this function. Maybe we can install IC5033 on Solaris (x86) next year.
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