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Recent content by hw2000

  1. H

    Command in Design Compiler to get least delay

    So, my current process is the way to do it, right? Maybe I can also write a script that will reduce the delay by 10% until its not possible anymore.
  2. H

    Command in Design Compiler to get least delay

    Hi Everyone, I have a purely combinational logic that I want to synthesize. I want to get the least delay possible on this delay. For that reason, I am using the following tcl script. set search_path {./../benchmark/hyb_both/ \...
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