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Re: what these two word mean? PID and PI in dc-dc compensati
P means proportional, such as a resistor makes the feedback compensation loop,Vout/Vin=-Rf/R1.
I means integral, such as a capacitor makes the feedback compensation loop, Vout=(-1/(R1*C))*∫Vin dt, or Vout=-1/(S*R1*C)*Vin.
D means...
Re: the Hspice simulation and the Spectre simulation differe
Your question does not have been sufficiently described!
When u simulate what parameter with Spectre and Hspice, the result is different !
Normally, the simulation result of spectre and hspice does not have big difference. Maybe u...
comparator hysteresis calculation
Hi teachers:
i have read the hysteresis comparator in the book "CMOS Analog Circuit Design", the detailed description is in the picture 1. But i cann't understand the calculation of the upper and lower trip point, my calculation is following:
When the inverter...
In my viewpoint, the LDO structure should be the same as the picture. The output has only one large capacitor Cb, and this Cb capacitor equates the series of a capacitor and a ESR. The effect of Cb is to generate a zero and raise the phase margin of loop, so stabilize the whole loop.
First, u charge the capacitor with a constant current "I", then discharge the capacitor with the same constant current "I". Of course, u must accurately control the time of charge and discharge under the 5V peak voltage!
Re: the op problem
I feel your DC operation point is somewhat problem, pls post the schematic of op and plot the open loop ac response curve of the op!
vce saturation
When the BJT is in the saturation, the Vce(sat) means the voltage difference between the Collector and Emitter at the spec. "Ic" current value. The value of Vce(sat) have relation to Ic(sat) and the collector resistance "rc".
Re: What are the advantage and disadvantage of CMOS technolo
Pls read the book " Analysis and Design of Analog Integrated Circuits" ! In this books, it has a detailed description.
Utilizing spectre simulator and the models file of 5V standard CMOS process , a nmos transistor is simulated, and the DC operation point of this nmos transistor is printed in the picture. Under the condition of normal operation state, i have some doubts concerning its DC parameters:
1. Why is...
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