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Dear Sir:
Could someone tell me why in some of the high speed cirucit design has the feedback loop, even the loop didn't have the compensation element.
In the other words, the circuits use the unstabled negative feedback.
What's the different of positive feedback and unstabled negative...
Dear all
I would like to simulate one huge ( analog+digital) circuit,
but it will take many time to do that in HSPICE.
I have tried Hsim, but it still take many time.
Does any one has the good idea or good tool to do the job?
How do you to simuilate when you meet a huge circuit and integrate...
Dear all:
I have a question. When a circuit includes two closed loops, which one will decide the loop stability and the circuit characteristics? High bandwidth loop decides it, or low bandwidth one?
Please help me to answer the question, thanks!
Re: Backend Process
The backend process include:
Circuit design, circuit synthesize, layout, P&R(Place and route), pin assignment
The backend support include:
P&R(Place and route), pin assignment
Re: Bandgap Opamp
In my opinion, the bandgap opamp bandwidth is not important,
because the bandgap just process the DC signal, but its gain is very important.
The opamp DC gain relatice to its input offset and it should be as small as possible.
To generate the 25MHz Frequency, why not try to use the pre-divider divide by 11,
and the loop-divider divide by 23?
By the way, the output frequency will be
12MHz X 23 /11 ≈25MHz
Re: How to generate a dynamic frequency square waveform in H
Yes, it work. Thanks for your help.
I use the VCO to generate the pattern. It work very well.
Dear all:
I would like to generate a square waveform with the ferquency changed from 99M to 100M among 15us in HSPICE environment.
But I have try many methods, I still can't generate the waveform.
:cry:
Any one have the idea to generate the waveform?
Re: decoupling capacitor
It is used to avoid the bounding wire noise.
Usually the capacitor is the more the better, but it will occupy your core circuits area. Use the capacitor to your analog power is better.
vco ac
Dear all :
I want to simulate the VCO(the delay cell is fully differential type) ac response, but I don't have any idea to do that.
Can I use the method of the fully differential op to do the simulation?
Where can I find the fully differential op simulation method?
Re: Question about PLL
Maybe you can try to add some conditions into the run file.
For example, add the power ramp (from 0 to vdd) or add the interference in the
power rail to model the real environment.
If your circuit can't osc with above conditions, maybe it have some unknow side effect.
dll false lock 1.5t 0.5t
Dear all:
I am a DLL-disign newer. I have read some papers about the DLL,
but I still don't know Why the DLL locking range is limited in the range
of 0.5T ~ 1.5 T.
Can any export answer the question for me, or where can I find the reference?
Thanks!
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