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I'am designing this chip. If the tranditional GGNMOS is used. When the input voltage is higher than 5V or lower than 0V, the input signal(±20V) will be clamped.
Sorry，I‘am designing this chip. The ESD voltage is 8kV. And the input voltage of the chip is ±20V. The problem is when the input voltage is higher than 5V or lower than 0V. The tranditional ESD circuit will clamp the voltage. so I need design a new ESD circuit to accept ±20V input voltage。
My chip is a single suppy with 5V and 0V ground.
But sometimes the input signal is up to ±20V，the tranditonal GGNMOS ESD will suffer big leakage (body to drain).
Is there any ESD architecture to meet this spec?
Thanks
Thanks for your advise and reference paper.
I have checked the parasitic. The post_sim result is about 70dB, and no missing code in 2048 or 256. My process is TSMC180nm ELL.
I have done a lot of caculation and matlab modeling.
I find that if the MSB cap with an err of 1/512, the MSB-1 cap with...
The 1st attached pic is the FFT result. The 2nd one is DNL and INL
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I dont know it's due to mismatch of the caps in the CADC or comparator or any other reasons?
I have designed a 12 bit SAR ADC with CDAC. There are a 4-bit MSB section and a 8bit LSB section in the CDAC. The architecture of comparator is 3-stage pre-amplifier+latch,whose VCM is generated by a resistor ladder. The spec is 125sps(2Mhz CLK) .
I tested the chip with input of 1.1kHz and 1Mhz...
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