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Hi everyone,
In synopsys design compiler, I only want to use several cells during optimization. I know "set_dont_use", but this command is too long and complex since I only want to use 10 cells... Is there any opposite command of "set_dont_use" something like "set_only_use" in synopsys design...
Hello,
the input wave is trapezoidal wave, rise time=30ps, fall time=30ps,plateau is 20ps,with amplitude=500m, it is the input signal of a 1bit adder's carry_in, so the pulse width of trapezoidal wave is 50ps.
The output as shown in the figure, is the wave occurs at carry_out. I need to record...
Hi, thanks for reply. Yes I know this "pulse" is really irregular... and I'm now looking for how can I approximate this irregular wave into a square wave.
Hello everyone,
I'm trying to inject pulse with different pulse width and height in to my adder circuit though carry_in, and record the height/width of pulse occurs at carry_out, and then build regression model... This is background.
I'm facing some troubles, in simulation I get a lot of...
Hallo everyone,
Im very new to sv and I have a quite simple question.
I have 3 module now, lets say there a module_1,module_2 and module_3.
Module_1(input a_1,output a_1);
module_2(input a_2,output a_2);
module_3(input a_3,output a_3);
Now I want to instance module_2 and module_3 in...
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