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Thank you for reply.
I am newbie in FPGA, sorry for poorly commented code.
What I need is:
At sync time of the VGA I need to write the frame data to SRAM.
when VGA in displaying mode I need to read the stored buffer from SRAM.
at reset I want to clear the buffer in SRAM.
What I did is:
At...
Hello guys,
I have problem in using sram as frame buffer
I have tried the following code but i got random pixel where I expect to get black screen with one red dot in the center.
I write on sram at sync. time
code for writing and reading from SRAM
// SRAM_control
reg [19:0] addr_reg...
What does WR1_LENGTH means here
//SDRam Read and Write as Frame Buffer
Sdram_Control u7 (
.RESET_N(KEY[0]),
.CLK(sdram_ctrl_clk),
// FIFO Write Side 1
.WR1_DATA({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
.WR1(sCCD_DVAL),
.WR1_ADDR(0),
`ifdef VGA_640x480p60
.WR1_MAX_ADDR(640*480/2)...
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