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Hi guys, I have compiled my VHDL coding in Quartus II and proceeded to SignalTap for simulation. However, when I tried to click 'run analysis' button under 'Processing' tab in SignalTap II Logic Analyzer each time it generates a new waveform.
I have verified my design in Modelsim and it works...
Guys, I managed to solve the problem by using sine wave block under signal processing blockset in Simulink. Simulink HDL Coder will help to generate the VHDL coding based on the Simulink model.
Thanks for the help.
There's a megafunction in Quartus II called NCO that can help to generate VHDL coding for sine wave but what I want to implement into the FPGA board is generating the end waveform of a sum of cosine waves of different harmonics. I have done it in MATLAB, so now I want to do on my DE1 board.
I'm currently dealing with my final year project that requires me to do FPGA implementation of generating 15-harmonics cosine wave with different phase shifts. Can anyone help me with the VHDL/Verilog coding? My project is related to crest factor reduction.
I'm using Altera DE1 board.
Please...
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