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Recent content by hhplay

  1. H

    Do i suit to be an analog IC designer?

    It is not easy but you still can be!
  2. H

    Using very long path in MOS gate without current flow

    Re: current and voltage Don't forget leakage current. Especially in 65nm.
  3. H

    how does the feedback affect the circuit noise performance?

    Re: how does the feedback affect the circuit noise performan I believe feedback system will reshape your noise. In fact, PLL is a feedback system which changes your input noise.
  4. H

    How to equate one terminal to another during Cadence LVS run?

    Re: cadence LVS Also in Assura, there is a "use joint net" function or something like that. You can use that function to do LVS
  5. H

    Post Layout Simulation (Back-annotation) - Cadence Spectre

    post-layout simulations on spectre You can use either config or simply insert your extracted view before your schematic view in your "analog enviroment" settings, and then run your simulation as before. Cheers!
  6. H

    a left zero before the second pole, is the system stable?

    Re: a left zero before the second pole, is the system stable Left zero helps your circuit to be stable. Be careful of your phase margin. It is not big enough!
  7. H

    The best RF design book?

    Totally agree with you!

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