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Recent content by hg527

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    24-bit width input data converted to 32-bit width data

    Hi Alex: Thanks for your reply once and again. Your answer is very clear. I think it is correct under the situation of data acquisition,especially samping the AD convertor. But under some special situation, maybe there are some other methods. if you are interested in the subject, you can check...
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    24-bit width input data converted to 32-bit width data

    Hi TrickyDicky: thank you for your reply. I think I understand you. I describe my project as below, and look for your advice. I use FPGA to acquire the input data which is 24-bit width at a frequency of 50MHz. But the data must be provided to another module with 32-bit data width. I use two...
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    24-bit width input data converted to 32-bit width data

    Thanks. what I mean is ,for example, the sram write data is data_wr[31:0]={0000,0000,valid data}. But in fact, I want the read data is data_rd[31:0]={all valid data}. how can i get it? My original question is how can I convert the data_in[23:0] to data_wr[31:0] with all valid data bits and...
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    24-bit width input data converted to 32-bit width data

    Thank you for you reply. Indeed, after storing the input data to SRAM, I need read the data out with width of 32-bit. If add '0' to MSB, it will produce error except of the conversion of 24-bit to 32-bit.
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    24-bit width input data converted to 32-bit width data

    Hello everybody: I want to capture the input data and store them into SRAM. The Width of the input data is 24-bit at a speed of 50MHz, but the SRAM input data width is 32-bit. So, how can I do? I put forword the following solutions: 1) Using serials-in-parallel-out (SIPO) and PISO. Capture the...
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    single ended clock connected to the N-side differential pin

    Re: single ended clock connected to the N-side differential Dear TA37: Thank you for your replay. I think maybe you are right. I will try it and hope it will work. Xinlin’s manual says: “Each differential global clock pin pair can connect to either a differential or single-ended clock on the...
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    single ended clock connected to the N-side differential pin

    Hi,everyone: I use Virtex5 and ISE10.1. I connect one chip’s single ended clock to the N-side of clock capable pins of Virtex5 FPGA by accident on my PCB board. But Xilinx’s manual demands :“1)Do not connect a single ended clock to the N-side of the differential clock pair of pins, for...

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