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cmos inductor
hello, everyone.
now i have a EM-simulation question about CMOS inductor with different substrate resistivity
the inductor layouts (N=4.5, W=10um, S=2um and Rin=60um) and process parameters are same and the substrate resistivity is 1000, 100, 10, 1, 0.1 respectively, the unit is...
so how can i get a variable gain in PA, couple a power detector at the output port of the power stage of PA and feed back to the input port of the drive stage of PA, and when the output power is more or less than 28dBm, then make the input power decrease or increase ?!
gsg layout
i think you can connect the two ground pins together using some metal lines, but if you don't do this, that's no problem.
practically when you test your devices or circuits, the two ground pins of the G-S-G pad would be contacted to the two ground terminals of the probe...
in cdma pa design, the input power is not constant when the output power is fixed (e.g. 28dBm). the input power generally vary from several -dBm to several +dBm.
so the question is how to make a stable output power when the input power is varied. anybody know some solutions?
thanks a...
Thanks.
but how can i get the quiescent current in a simulator, e.g. in @DS. and, if no input signal, that is like dc simulation. however, DC simulation is indepedent with max output power or modulation. expect an explanation.
ruggedness pa
hello, every1. in pa design, one of specifications is ruggedness no demage, the typical value is 10:1 & the unit is VSWR, but what meaning the "ruggedness no demage" is ? anybody can explain it for me
thanks a lot.
about a BJT model in @ds
I had downed a @ds model on a BJT with its s parameter data file from @gilent web site.
However, i don't know the s parameter derivated of the DIE model(bond pad capacitance included) or the SOT-143 plastic model.
who can help me?
thanks
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