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I am not sure if I understand the question, but as I see it the transitor will be in linear/triode mode until Vgs>Vth and Vds<(Vgs-Vth). If this is true node B will more or less folow node A.
BR Jerry
Hello CHL,
While delta-sigma or sigma-delta is in essence an averaging process the oversampling is not the only thing responsible for the ENOB.
For example only OSR improves the number ob bits from n to ENOB=n+0.5*log2(OSR). Now this means that for a 5-bit gaing OSR of 1024 is needed.
Now if...
While not being a spice expert, a quick look at hspice manual https://cseweb.ucsd.edu/classes/wi10/cse241a/assign/hspice_cmdref.pdf
.HB Invokes the single and multitone harmonic balance algorithm for periodic
steady state analysis.
.HBAC Performs harmonic-balance–based periodic AC analysis...
For SC verification there are analysis such as pss, pac, pnoise ... https://www.designers-guide.org/analysis/sc-filters.pdf, which are available with spectre. I don't know what is available in spice and MULTISIM, but I am almost certain that there should be something similar.
PS: The final...
Hi je01911,
I tried to measure kT/C noise in the circuit you provided but got strange results and it did not converge.
I have attached a simple low pass filter, where we have two switches and a capacitor. The clock frequency is 10Mhz so the equivalent resistance should be approx 1Mohm with a...
Hi AMAS84,
In my last project I needed a non-overlapping clock generator for switch control in a SC circuitry. What I found was, that for adjusting dead-time I added additional buffers. I would usually start with minimum size (W/L) transistors and go from there, to control the rise and fall...
Hi sharezhao,
Please have a look at this articles **broken link removed** http://www.designers-guide.org/Forum/Attachments/schrier_tcas1_SC.pdf, hope it helps.
BR Jerry
Spectre and spice offer additional simulation like pss etc. The first example in google of PSS anylysis for PLL https://www.cadence.com/rl/Resources/conference_papers/ctp_cdnlivesv2007_Thibieroz.pdf
Hope this helps.
BR Jerry
For example if M2 is fully ON and M1 is OFF, the current trough M3 is 0, so current trough M4 is 0. This means that the voltage (charge) over (on) Cc will change, in this case depending on the current source which is realized with M5.
Simplified, you could write:
I=C*V/t => I/C=V/t
Hope this...
I would suggest you extend the transient simulation time so you have at least 2^16 samples of BS. Export the BS and do an FFT. For example with a 2 MHz clock for 2^16 you need a simulation time of aprox. 32.8 ms.
BR Jerry
Could you also produce the phase plot?
Why do you think that the circuit will oscillate? When doing the tran simulation, did you confirm that the circuit oscilated?
BR Jerry
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