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The code is a sample of transfer from 16bit 622MHz to 32bit 311MHz.
You can do it in two steps.
first, deserdes from 16bit 622MHz to 64bit 155M with the code attached.
second, deserdes 64bit 155Mhz to 256bit 39Mhz with your own way (daul port ram or Flip-flop divider).
I think you have missunderstood me. In ur figure, all ur need to do is to transfer high speed 16bit data to low speed 256bit. It don't need FPGA's RocketIO to SERDES/DESERDES which is called 'hard SERDES'. The file I had attached a couple days ago is using technic called DPA(dynamic phase...
xilinx oddr
Fpga implementation is usually use to verify the ASIC design. If u want to tape out a chip, Fpga design is the frist step.
However, if u don't want to make a chip totally, I think u had better migrate from V4 to Hardcopy.
I just finished a case of deserialize from 16bit_622MHz to 32bit_311M. You can refer to the attachment. The source code isn't inclued in file which is delivered by Xilinx FAE.
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