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Ok, now we decided to design out own flip chip pad, area is the major concern, so if anyone have done that before, please please let me know and we can discuess it, thanks.
Not exactly I think, for digital IO, you need IO cell to drive the IO, maybe only a buffer, but you need it and you can't just connect it to the bump. Besides, you need ESD protection for each IO, you can't just connect the signals to outside. Anyone have any idea about it?
Does any know about flipchip IO PAD? In our cadence design kit, I only see IO pad cell for wirebond chip, I think it's not suitable for flipchip, so anyone who has designed a flip chip PAD please give me some information, thanks. I searched google, no article related the flipchip IO cell design...
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