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Recent content by hdlcohen

  1. H

    systemverilog assertion

    Use either of these property operators The case property operator has the following form: [1] case ( expression_or_dist ) property_case_item { property_case_item } endcase property_case_item::= expression_or_dist { , expression_or_dist } : property_statement | default [ : ]...
  2. H

    Are systemverilog assertions synthesizable by Synopsys Design Compiler

    SVA concurrent are not synthesizable. They are used only for verification. In fact, it is generally preferred that SVA assertions be put in a module bound to a DUT so as isolate the verification code from RTL,and to avoid resynthesis of good RTL code because of a timestamp change due to SVA...
  3. H

    Systemverilog assertion ....

    ap_b: assert property(@ (posedge clk) !$stable(b) && b==0 |=> b==2; /// if unstable(b) and b==0, then @net cycle b==2 ); -------------------------------------------------------------------------- Ben Cohen, Design and verification expert (310) 997-2187...
  4. H

    Are systemverilog assertions synthesizable by Synopsys Design Compiler

    <Could you tell which assertions are synthesizable?> None. There is such a thing as "Assertion Synthesis", but that takes rtl and coverts it into assertions. See **broken link removed** Ben Cohen SystemVerilog.us
  5. H

    Are systemverilog assertions synthesizable by Synopsys Design Compiler

    Re: Are systemverilog assertions synthesizable by Synthesis tools NO. assertions are used for verification. Synthesis if for conversion of RTL into gates. Conversion from SVA to gates is not supported. Ben Cohen -------------------------------------------------------------------------- Ben...
  6. H

    How we call a pipeline with combinatoryl logic?

    Re: How we call that ? I still see it as "pipeline". Pipeline can have combinational logic en between registers. The whole purpose of pipelining is to speed up the clock cycle. -------------------------------------------------------------------------- Ben Cohen (831) 345-1759...
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    Free SV editor "sveditor" with "eclipse"

    Re: Free SV editor "sveditor" with "eclipse&a Yes, I would consider it, even if you like another editor (e.g., emacs) as your main editor. It's easy to do searches across the directory, see multiple files, and make changes, enter tasks (things to flag, as links to the file), etc. I am still...
  8. H

    how to display text in vhdl?

    You can use the report report "End of file " & ControlFile_g & " Pseudo random Transactions" severity Note; But you can also use the textio Example (from old code) use Work.Image_pkg.all; // Useful package // see...
  9. H

    Free SV editor "sveditor" with "eclipse"

    I downloaded and installed sveditor running in the exclipse environment. Let first preface that I am an emacs user. However, this editor does have some very nice features, such as searching for a word* in a directory, auto-completion, colorization of SystemVerilog keywords, and some content...
  10. H

    DvCon: Experiencing Checkers for a Cache Controller Design

    Paper and slides and code can be downloaded from https://systemverilog.us/DvCon2010/ _________________ Ben Cohen https://www.systemverilog.us/ * SystemVerilog Assertions Handbook, 2nd Edition, 2010 * A Pragmatic Approach to VMM Adoption * Using PSL/SUGAR ... 2nd Edition * Real Chip Design...
  11. H

    Which assertion language is good to start with - PSL or SVA?

    Re: PSL or SVA Having written books on both languages, I definitely prefer SVA it has a lot of very nice features. In fact, we just came out with a new book "SystemVerilog Assertions Handbook, 2nd Edition" that includes the IEEE 1800-2009 updates. For more information, see...
  12. H

    What's the best VHDL/Verilog/SystemVerilog editor?

    I haven't used the AUTO feature of verilog. However, SystemVerilogmade life a lot easier on things like the port declaration, and sensitivity list (like the always_comb). In any case, teh completion mode of emacs is great. On typing tools, I use Texter, and highly recommend it. It works on...
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    What's the best VHDL/Verilog/SystemVerilog editor?

    I used both extensively. The VHDL mode has a beautify buffer that fixes up all the indentations. It also has a create testbench. My copy of that is at https://SystemVerilog.us/vhdl-mode.el https://SystemVerilog.us/vhdl-mode.elc Ben
  14. H

    What's the best VHDL/Verilog/SystemVerilog editor?

    **broken link removed** Add SystemVerilog Snippets for Emacs
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