Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello FvM
here is my code
// condition for overflow:
//-the ALU is performing addition or subtraction (ALUControl1 = 0)
//-A and Sum have opposite signs, as detected by the XOR gate
//-either A and B have the same sign and the adder is performing addition (ALUControl0 = 0) or A and B have...
Hello,
I had those errors, i tried a lot to correct but i didn't get any thing
** Error: (vlog-13069) C:/Users/hbelk/Desktop/Homework_4/Homework_4.sv(26): near "=": syntax error, unexpected '=', expecting ++ or --.
** Error: (vlog-13069) C:/Users/hbelk/Desktop/Homework_4/Homework_4.sv(31)...
Hello,
there are conditions for overflow
// condition for overflow:
//-the ALU is performing addition or subtraction (ALUControl1 = 0)
//-A and Sum have opposite signs, as detected by the XOR gate and as detected by the XNOR gate
//-either A and B have the same sign and the adder is performing...
hello,
I'm trying to implement a 32 bit ALU with Input a,b and output Result and 4 bit ALUFlags in system verilog.
the problem for me is that i Don't know how to implement the ALUFlags especially the Carryout.
should I use the one bit adder/sabstract .
Could any one help me
thank you in advance...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
