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Alright! So just to be as thorough as possible for future reader, I'll post the correct schematics and the equations below.
gm1=0.0007640S
gm2=0.00342857S
gm3=0.0356436S
KCL@V1: v1/1000,000-0.001/1000,000=0
KCL@V2: gm1*(v1-v3)+v2/2000=0
KCL@V3: -gm1*(v1-v3)+gm2*v3+v3/752=0
KCL@V4...
I have corrected the schematics, and applied a 1nA current source to the input.
I'll set these equations up in Matlab now, to solve for all the V*s
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So the voltage gain V5/V1=-0.0380364V/0.002V=-19.0182V/V
So shouldnt that give us...
I think I might need a little help with getting the equations right with the nodal analysis first, im working on them right now.
Well, the software for drawing the circuits is just something I googled which was easy to learn, CircuitLab
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The first attempt at the nodal...
I do have an instructor for this course, and I will ask him about this, but he won't reply until monday. The slope is the gm-value for the transistor.
Maybe, we should have assumed the gm-value was 4ms for both of the transistors, but I don't know for sure.
So, should I begin my nodal...
Sorry for taking so long.
I honestly have now idea why the given value and the calculated value differs so much. Is the problem faulty or have I made a mistake along the way?
This is the connected small-signal model we got;
With the values: RG=1MΩ RS=15kΩ RD=2kΩ R1=791.7Ω R4=1708.3Ω...
Alright, common gate is fine.
Then I have remade the common-drain according to your drawing:
And then the common-emitter:
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Maybe the VGS should be Vbe in the common-emitter.
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Here are the small-signal models with the nodes numbered:
Common-drain...
To try and answer your question, this is a school exercise and this amplifier will not be built.
If you're irretated that the circuit doesn't make any sense, be mad at my teacher! ;-)
I tried to do as you told me, regarding the BJT and so on. I just want to have it confirmed that the small-signal models are correct, before labelling the nodes.
Common-drain
Common-gate
Common-emitter
Well, after watching some videos about makin a small signal model, the model for the common source transistor should be like this:
I'm working on the rest as we speak..
Here is the final schedule we got;
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Not entirely sure about the small-signal model...
Yes, ofcourse I realized this wasn't correct. I just got so frustrated that I couldn't come up with a answer that makes sense that I left it there.
Rs*IDSS*(1-UGS/Up)²=-UGS, Where Rs=15kΩ IDSS=9mA Up=-3.5V
<=> 15000*(9*10^-3)*(1-(UGS/(-3.5)))^2=-UGS, I get two values; UGS1= -4.111V UGS2=...
I read at a FET biasing page;
The operating point (that is zero signal ID and VDS) can easily be determined from equation and equation given below :
VDS = VDD – ID (RD + RS)
Where my values are; VDD: 10V ID=IDSS=9mA RD=2kΩ RS=15kΩ
VDS=10-(9*10-³)*(2000+15000)=-143V...
So it should be R4=(12-5.16667)/0.004=1708.3325Ω
So if I get you right I should take the derivative of iD=IDSS*(1-uGS/Up)² with respect to uGS.
With the given values inserted this equals: 0.00514286+0.00146939uGS, when I put my uGS in it, it gives me gm=0.00342857=3.4286mS
Haha, it's the...
Is it correct to assume that the value for R4 should be 10/0.004=2500Ω?
Just looking briefly at what transconductance is the formula for it is gm=Iout/Vin, this should result in: UGS=Vin=-1.16667V IDQ=Iout=0.004A => 0.004/-1.16667=-3.4286mS
Here's the schedule sofar, not assuming R4 is...
With the given values; Up=-3.5V IDSS=9mA and ID=0.004A
UGS=(1-√(ID/IDSS))Up
Gives UGS=-1.16667V
Should give us US=2V-UGS => US=3.16667V
And with ohms law 3.16667/0.004=791.6675Ω
Thanks to everyone for showing such great interest in this thread, although you lost me abit in the latest comment.
Listening to The Electrician, I get R3=10V/125µA=80kΩ.
Here's a schedule with the known values.
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