Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by harshahari

  1. H

    No clock in design error occur in icc

    Hi All while doing CTS in icc compiler i got error "no clock in design" . can any one help where is the problem and how to move forward. Harish
  2. H

    Input reference library in synopsys ic compiler tool

    what can we give in input reference library in synopsys ?Is this is optional or compulsory to take for synopsys tool(IC compiler)?
  3. H

    Prime time tool input files

    Actually first time i am using the prime time tool. That's why i am raising the questions in this forum.We need .sdf,sdc,netlist.v,.db files to run the prime time tool.For that i want some samples files what we need to run the prime time tool please provide any one.i checked in few websites for...
  4. H

    Prime time tool of Synopsys

    How can we load the input files to prime time tool ?
  5. H

    Synthesis in design vision

    What are the libraries required to set up in design topo mode?
  6. H

    Static timing analysis

    As per my understanding we want to do STA after synthesis and after placement and after routing. that's why i sent post like that.
  7. H

    Static timing analysis

    what are libraries need to do design in icc compiler?
  8. H

    Simulation and synthesis.

    Yaa ok now my question is if we synthesis the code with directives then we got errors and if we delete the those directives ('ifndef,ifdef) fromcode then becoming output is correct or not?
  9. H

    Simulation and synthesis.

    Yaa ok but while synthesis the code the errors are occurred then how can i correct these errors.
  10. H

    Simulation and synthesis.

    I have mentor tools for simulation and synthesis the verilog code in that tools i i have got some errors while run the code those are token 'ifndef' was not defined and no 'ifndef' was not found to match 'endif'. and now tell me what is the meaning of 'ifnedf' and how to correct the these errors?
  11. H

    Dog leg technique in routing

    In routing we have dog leg technique in this we can take the additional column for avoid the overlapping now my question is due to dog leg technique channel height is reduced or not ? if it is reduced please tell me how ?
  12. H

    Clock tree synthesis

    What is skew and how to identify the skew either clock signal to clock signal or clock signal to data signal or data signal to data signal?

Part and Inventory Search

Back
Top