Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
There are few questions about this interesting inverter.
What is the principle of output voltage adjustment?
Me and my friend have made it and found that when you is rising your input (accumulator) voltage, the output voltage is reaching 235V and then swithcing back to 230V ... next rising to...
delay in cpld
Hi!
I am newbie in CPLD, so excuse me for strange question.
I need to add small delay in MAX7000S output - near 50-60 nS. There are no clock logic there in my project. I was trying to add chain of simple elements - pairs of invertors, but seems compiler is deleting them during...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
